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[RISCV] Add Smcsrind and Sscsrind extension (#93952)
Specification link: https://github.com/riscv/riscv-isa-manual/blob/main/src/indirect-csr.adoc Some CSRs (`*ireg` and `*iselect`) in Smcsrind/Sscsrind extensions are originally defined as part of the Smaia/Ssaia extensions and are already supported in LLVM. The missing CSRs (`*ireg2` to `*ireg6` for `m`, `s`, and `vs`) are added in this PR.
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clang/test/Preprocessor/riscv-target-features.c

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@@ -28,13 +28,15 @@
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// CHECK-NOT: __riscv_shvstvecd {{.*$}}
2929
// CHECK-NOT: __riscv_smaia {{.*$}}
3030
// CHECK-NOT: __riscv_smcdeleg {{.*$}}
31+
// CHECK-NOT: __riscv_smcsrind {{.*$}}
3132
// CHECK-NOT: __riscv_smepmp {{.*$}}
3233
// CHECK-NOT: __riscv_smstateen {{.*$}}
3334
// CHECK-NOT: __riscv_ssaia {{.*$}}
3435
// CHECK-NOT: __riscv_ssccfg {{.*$}}
3536
// CHECK-NOT: __riscv_ssccptr {{.*$}}
3637
// CHECK-NOT: __riscv_sscofpmf {{.*$}}
3738
// CHECK-NOT: __riscv_sscounterenw {{.*$}}
39+
// CHECK-NOT: __riscv_sscsrind {{.*$}}
3840
// CHECK-NOT: __riscv_ssstateen {{.*$}}
3941
// CHECK-NOT: __riscv_ssstrict {{.*$}}
4042
// CHECK-NOT: __riscv_sstc {{.*$}}
@@ -1403,6 +1405,22 @@
14031405
// RUN: -o - | FileCheck --check-prefix=CHECK-SSAIA-EXT %s
14041406
// CHECK-SSAIA-EXT: __riscv_ssaia 1000000{{$}}
14051407

1408+
// RUN: %clang --target=riscv32 \
1409+
// RUN: -march=rv32ismcsrind1p0 -E -dM %s \
1410+
// RUN: -o - | FileCheck --check-prefix=CHECK-SMCSRIND-EXT %s
1411+
// RUN: %clang --target=riscv64 \
1412+
// RUN: -march=rv64ismcsrind1p0 -E -dM %s \
1413+
// RUN: -o - | FileCheck --check-prefix=CHECK-SMCSRIND-EXT %s
1414+
// CHECK-SMCSRIND-EXT: __riscv_smcsrind 1000000{{$}}
1415+
1416+
// RUN: %clang --target=riscv32 \
1417+
// RUN: -march=rv32isscsrind1p0 -E -dM %s \
1418+
// RUN: -o - | FileCheck --check-prefix=CHECK-SSCSRIND-EXT %s
1419+
// RUN: %clang --target=riscv64 \
1420+
// RUN: -march=rv64isscsrind1p0 -E -dM %s \
1421+
// RUN: -o - | FileCheck --check-prefix=CHECK-SSCSRIND-EXT %s
1422+
// CHECK-SSCSRIND-EXT: __riscv_sscsrind 1000000{{$}}
1423+
14061424
// RUN: %clang --target=riscv32 \
14071425
// RUN: -march=rv32ismcdeleg1p0 -E -dM %s \
14081426
// RUN: -o - | FileCheck --check-prefix=CHECK-SMCDELEG-EXT %s

llvm/docs/RISCVUsage.rst

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@@ -100,13 +100,15 @@ on support follow.
100100
``Shvstvecd`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
101101
``Smaia`` Supported
102102
``Smcdeleg`` Supported
103+
``Smcsrind`` Supported
103104
``Smepmp`` Supported
104105
``Smstateen`` Assembly Support
105106
``Ssaia`` Supported
106107
``Ssccfg`` Supported
107108
``Ssccptr`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
108109
``Sscofpmf`` Assembly Support
109110
``Sscounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
111+
``Sscsrind`` Supported
110112
``Ssstateen`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
111113
``Ssstrict`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
112114
``Sstc`` Assembly Support

llvm/docs/ReleaseNotes.rst

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@@ -157,7 +157,7 @@ Changes to the RISC-V Backend
157157
* Processors that enable post reg-alloc scheduling (PostMachineScheduler) by default should use the `UsePostRAScheduler` subtarget feature. Setting `PostRAScheduler = 1` in the scheduler model will have no effect on the enabling of the PostMachineScheduler.
158158
* Zabha is no longer experimental.
159159
* B (the collection of the Zba, Zbb, Zbs extensions) is supported.
160-
* Added smcdeleg and ssccfg extensions to -march.
160+
* Added smcdeleg, ssccfg, smcsrind, and sscsrind extensions to -march.
161161

162162
Changes to the WebAssembly Backend
163163
----------------------------------

llvm/lib/Target/RISCV/RISCVFeatures.td

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Original file line numberDiff line numberDiff line change
@@ -855,6 +855,13 @@ def FeatureStdExtSsaia
855855
"'Ssaia' (Advanced Interrupt Architecture Supervisor "
856856
"Level)">;
857857

858+
def FeatureStdExtSmcsrind
859+
: RISCVExtension<"smcsrind", 1, 0,
860+
"'Smcsrind' (Indirect CSR Access Machine Level)">;
861+
def FeatureStdExtSscsrind
862+
: RISCVExtension<"sscsrind", 1, 0,
863+
"'Sscsrind' (Indirect CSR Access Supervisor Level)">;
864+
858865
def FeatureStdExtSmepmp
859866
: RISCVExtension<"smepmp", 1, 0,
860867
"'Smepmp' (Enhanced Physical Memory Protection)">;

llvm/lib/Target/RISCV/RISCVSystemOperands.td

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Original file line numberDiff line numberDiff line change
@@ -382,6 +382,12 @@ def SEED : SysReg<"seed", 0x015>;
382382
// Machine-level CSRs
383383
def : SysReg<"miselect", 0x350>;
384384
def : SysReg<"mireg", 0x351>;
385+
foreach i = 2...3 in {
386+
def : SysReg<"mireg"#i, !add(0x350, i)>;
387+
}
388+
foreach i = 4...6 in {
389+
def : SysReg<"mireg"#i, !add(0x351, i)>;
390+
}
385391
def : SysReg<"mtopei", 0x35C>;
386392
def : SysReg<"mtopi", 0xFB0>;
387393
def : SysReg<"mvien", 0x308>;
@@ -397,6 +403,12 @@ def : SysReg<"miph", 0x354>;
397403
// Supervisor-level CSRs
398404
def : SysReg<"siselect", 0x150>;
399405
def : SysReg<"sireg", 0x151>;
406+
foreach i = 2...3 in {
407+
def : SysReg<"sireg"#i, !add(0x150, i)>;
408+
}
409+
foreach i = 4...6 in {
410+
def : SysReg<"sireg"#i, !add(0x151, i)>;
411+
}
400412
def : SysReg<"stopei", 0x15C>;
401413
def : SysReg<"stopi", 0xDB0>;
402414
let isRV32Only = 1 in {
@@ -411,6 +423,12 @@ def : SysReg<"hviprio1", 0x646>;
411423
def : SysReg<"hviprio2", 0x647>;
412424
def : SysReg<"vsiselect", 0x250>;
413425
def : SysReg<"vsireg", 0x251>;
426+
foreach i = 2...3 in {
427+
def : SysReg<"vsireg"#i, !add(0x250, i)>;
428+
}
429+
foreach i = 4...6 in {
430+
def : SysReg<"vsireg"#i, !add(0x251, i)>;
431+
}
414432
def : SysReg<"vstopei", 0x25C>;
415433
def : SysReg<"vstopi", 0xEB0>;
416434
let isRV32Only = 1 in {

llvm/test/CodeGen/RISCV/attributes.ll

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@@ -112,6 +112,8 @@
112112
; RUN: llc -mtriple=riscv32 -mattr=+zcmop %s -o - | FileCheck --check-prefix=RV32ZCMOP %s
113113
; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s
114114
; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
115+
; RUN: llc -mtriple=riscv32 -mattr=+smcsrind %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCSRIND %s
116+
; RUN: llc -mtriple=riscv32 -mattr=+sscsrind %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCSRIND %s
115117
; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s
116118
; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
117119
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
@@ -248,6 +250,8 @@
248250
; RUN: llc -mtriple=riscv64 -mattr=+zcmop %s -o - | FileCheck --check-prefix=RV64ZCMOP %s
249251
; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s
250252
; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
253+
; RUN: llc -mtriple=riscv64 -mattr=+smcsrind %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCSRIND %s
254+
; RUN: llc -mtriple=riscv64 -mattr=+sscsrind %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCSRIND %s
251255
; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s
252256
; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
253257
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
@@ -390,6 +394,8 @@
390394
; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop1p0"
391395
; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
392396
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
397+
; RV32SMCSRIND: .attribute 5, "rv32i2p1_smcsrind1p0"
398+
; RV32SSCSRIND: .attribute 5, "rv32i2p1_sscsrind1p0"
393399
; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
394400
; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
395401
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
@@ -525,6 +531,8 @@
525531
; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop1p0"
526532
; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
527533
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
534+
; RV64SMCSRIND: .attribute 5, "rv64i2p1_smcsrind1p0"
535+
; RV64SSCSRIND: .attribute 5, "rv64i2p1_sscsrind1p0"
528536
; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
529537
; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
530538
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"

llvm/test/MC/RISCV/attribute-arch.s

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@@ -315,6 +315,12 @@
315315
.attribute arch, "rv32i_ssaia1p0"
316316
# CHECK: attribute 5, "rv32i2p1_ssaia1p0"
317317

318+
.attribute arch, "rv32i_smcsrind1p0"
319+
# CHECK: attribute 5, "rv32i2p1_smcsrind1p0"
320+
321+
.attribute arch, "rv32i_sscsrind1p0"
322+
# CHECK: attribute 5, "rv32i2p1_sscsrind1p0"
323+
318324
.attribute arch, "rv32i_smcdeleg1p0"
319325
# CHECK: attribute 5, "rv32i2p1_smcdeleg1p0"
320326

llvm/test/MC/RISCV/hypervisor-csr-names.s

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Original file line numberDiff line numberDiff line change
@@ -536,6 +536,76 @@ csrrs t1, vsireg, zero
536536
# uimm12
537537
csrrs t2, 0x251, zero
538538

539+
# vsireg2
540+
# name
541+
# CHECK-INST: csrrs t1, vsireg2, zero
542+
# CHECK-ENC: encoding: [0x73,0x23,0x20,0x25]
543+
# CHECK-INST-ALIAS: csrr t1, vsireg2
544+
# uimm12
545+
# CHECK-INST: csrrs t2, vsireg2, zero
546+
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x25]
547+
# CHECK-INST-ALIAS: csrr t2, vsireg2
548+
# name
549+
csrrs t1, vsireg2, zero
550+
# uimm12
551+
csrrs t2, 0x252, zero
552+
553+
# vsireg3
554+
# name
555+
# CHECK-INST: csrrs t1, vsireg3, zero
556+
# CHECK-ENC: encoding: [0x73,0x23,0x30,0x25]
557+
# CHECK-INST-ALIAS: csrr t1, vsireg3
558+
# uimm12
559+
# CHECK-INST: csrrs t2, vsireg3, zero
560+
# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x25]
561+
# CHECK-INST-ALIAS: csrr t2, vsireg3
562+
# name
563+
csrrs t1, vsireg3, zero
564+
# uimm12
565+
csrrs t2, 0x253, zero
566+
567+
# vsireg4
568+
# name
569+
# CHECK-INST: csrrs t1, vsireg4, zero
570+
# CHECK-ENC: encoding: [0x73,0x23,0x50,0x25]
571+
# CHECK-INST-ALIAS: csrr t1, vsireg4
572+
# uimm12
573+
# CHECK-INST: csrrs t2, vsireg4, zero
574+
# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x25]
575+
# CHECK-INST-ALIAS: csrr t2, vsireg4
576+
# name
577+
csrrs t1, vsireg4, zero
578+
# uimm12
579+
csrrs t2, 0x255, zero
580+
581+
# vsireg5
582+
# name
583+
# CHECK-INST: csrrs t1, vsireg5, zero
584+
# CHECK-ENC: encoding: [0x73,0x23,0x60,0x25]
585+
# CHECK-INST-ALIAS: csrr t1, vsireg5
586+
# uimm12
587+
# CHECK-INST: csrrs t2, vsireg5, zero
588+
# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x25]
589+
# CHECK-INST-ALIAS: csrr t2, vsireg5
590+
# name
591+
csrrs t1, vsireg5, zero
592+
# uimm12
593+
csrrs t2, 0x256, zero
594+
595+
# vsireg6
596+
# name
597+
# CHECK-INST: csrrs t1, vsireg6, zero
598+
# CHECK-ENC: encoding: [0x73,0x23,0x70,0x25]
599+
# CHECK-INST-ALIAS: csrr t1, vsireg6
600+
# uimm12
601+
# CHECK-INST: csrrs t2, vsireg6, zero
602+
# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x25]
603+
# CHECK-INST-ALIAS: csrr t2, vsireg6
604+
# name
605+
csrrs t1, vsireg6, zero
606+
# uimm12
607+
csrrs t2, 0x257, zero
608+
539609
# vstopei
540610
# name
541611
# CHECK-INST: csrrs t1, vstopei, zero

llvm/test/MC/RISCV/machine-csr-names.s

Lines changed: 70 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2443,6 +2443,76 @@ csrrs t1, mireg, zero
24432443
# uimm12
24442444
csrrs t2, 0x351, zero
24452445

2446+
# mireg2
2447+
# name
2448+
# CHECK-INST: csrrs t1, mireg2, zero
2449+
# CHECK-ENC: encoding: [0x73,0x23,0x20,0x35]
2450+
# CHECK-INST-ALIAS: csrr t1, mireg2
2451+
# uimm12
2452+
# CHECK-INST: csrrs t2, mireg2, zero
2453+
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x35]
2454+
# CHECK-INST-ALIAS: csrr t2, mireg2
2455+
# name
2456+
csrrs t1, mireg2, zero
2457+
# uimm12
2458+
csrrs t2, 0x352, zero
2459+
2460+
# mireg3
2461+
# name
2462+
# CHECK-INST: csrrs t1, mireg3, zero
2463+
# CHECK-ENC: encoding: [0x73,0x23,0x30,0x35]
2464+
# CHECK-INST-ALIAS: csrr t1, mireg3
2465+
# uimm12
2466+
# CHECK-INST: csrrs t2, mireg3, zero
2467+
# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x35]
2468+
# CHECK-INST-ALIAS: csrr t2, mireg3
2469+
# name
2470+
csrrs t1, mireg3, zero
2471+
# uimm12
2472+
csrrs t2, 0x353, zero
2473+
2474+
# mireg4
2475+
# name
2476+
# CHECK-INST: csrrs t1, mireg4, zero
2477+
# CHECK-ENC: encoding: [0x73,0x23,0x50,0x35]
2478+
# CHECK-INST-ALIAS: csrr t1, mireg4
2479+
# uimm12
2480+
# CHECK-INST: csrrs t2, mireg4, zero
2481+
# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x35]
2482+
# CHECK-INST-ALIAS: csrr t2, mireg4
2483+
# name
2484+
csrrs t1, mireg4, zero
2485+
# uimm12
2486+
csrrs t2, 0x355, zero
2487+
2488+
# mireg5
2489+
# name
2490+
# CHECK-INST: csrrs t1, mireg5, zero
2491+
# CHECK-ENC: encoding: [0x73,0x23,0x60,0x35]
2492+
# CHECK-INST-ALIAS: csrr t1, mireg5
2493+
# uimm12
2494+
# CHECK-INST: csrrs t2, mireg5, zero
2495+
# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x35]
2496+
# CHECK-INST-ALIAS: csrr t2, mireg5
2497+
# name
2498+
csrrs t1, mireg5, zero
2499+
# uimm12
2500+
csrrs t2, 0x356, zero
2501+
2502+
# mireg6
2503+
# name
2504+
# CHECK-INST: csrrs t1, mireg6, zero
2505+
# CHECK-ENC: encoding: [0x73,0x23,0x70,0x35]
2506+
# CHECK-INST-ALIAS: csrr t1, mireg6
2507+
# uimm12
2508+
# CHECK-INST: csrrs t2, mireg6, zero
2509+
# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x35]
2510+
# CHECK-INST-ALIAS: csrr t2, mireg6
2511+
# name
2512+
csrrs t1, mireg6, zero
2513+
# uimm12
2514+
csrrs t2, 0x357, zero
2515+
24462516
# mtopei
24472517
# name
24482518
# CHECK-INST: csrrs t1, mtopei, zero

llvm/test/MC/RISCV/supervisor-csr-names.s

Lines changed: 70 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -342,6 +342,76 @@ csrrs t1, sireg, zero
342342
# uimm12
343343
csrrs t2, 0x151, zero
344344

345+
# sireg2
346+
# name
347+
# CHECK-INST: csrrs t1, sireg2, zero
348+
# CHECK-ENC: encoding: [0x73,0x23,0x20,0x15]
349+
# CHECK-INST-ALIAS: csrr t1, sireg2
350+
# uimm12
351+
# CHECK-INST: csrrs t2, sireg2, zero
352+
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x15]
353+
# CHECK-INST-ALIAS: csrr t2, sireg2
354+
# name
355+
csrrs t1, sireg2, zero
356+
# uimm12
357+
csrrs t2, 0x152, zero
358+
359+
# sireg3
360+
# name
361+
# CHECK-INST: csrrs t1, sireg3, zero
362+
# CHECK-ENC: encoding: [0x73,0x23,0x30,0x15]
363+
# CHECK-INST-ALIAS: csrr t1, sireg3
364+
# uimm12
365+
# CHECK-INST: csrrs t2, sireg3, zero
366+
# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x15]
367+
# CHECK-INST-ALIAS: csrr t2, sireg3
368+
# name
369+
csrrs t1, sireg3, zero
370+
# uimm12
371+
csrrs t2, 0x153, zero
372+
373+
# sireg4
374+
# name
375+
# CHECK-INST: csrrs t1, sireg4, zero
376+
# CHECK-ENC: encoding: [0x73,0x23,0x50,0x15]
377+
# CHECK-INST-ALIAS: csrr t1, sireg4
378+
# uimm12
379+
# CHECK-INST: csrrs t2, sireg4, zero
380+
# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x15]
381+
# CHECK-INST-ALIAS: csrr t2, sireg4
382+
# name
383+
csrrs t1, sireg4, zero
384+
# uimm12
385+
csrrs t2, 0x155, zero
386+
387+
# sireg5
388+
# name
389+
# CHECK-INST: csrrs t1, sireg5, zero
390+
# CHECK-ENC: encoding: [0x73,0x23,0x60,0x15]
391+
# CHECK-INST-ALIAS: csrr t1, sireg5
392+
# uimm12
393+
# CHECK-INST: csrrs t2, sireg5, zero
394+
# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x15]
395+
# CHECK-INST-ALIAS: csrr t2, sireg5
396+
# name
397+
csrrs t1, sireg5, zero
398+
# uimm12
399+
csrrs t2, 0x156, zero
400+
401+
# sireg6
402+
# name
403+
# CHECK-INST: csrrs t1, sireg6, zero
404+
# CHECK-ENC: encoding: [0x73,0x23,0x70,0x15]
405+
# CHECK-INST-ALIAS: csrr t1, sireg6
406+
# uimm12
407+
# CHECK-INST: csrrs t2, sireg6, zero
408+
# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x15]
409+
# CHECK-INST-ALIAS: csrr t2, sireg6
410+
# name
411+
csrrs t1, sireg6, zero
412+
# uimm12
413+
csrrs t2, 0x157, zero
414+
345415
# stopei
346416
# name
347417
# CHECK-INST: csrrs t1, stopei, zero

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