disable isa xcr check. (#1512) (#1513)

* disable isa xcr check.

Author: xuhancn

csrc/cpu/CMakeLists.txt

@@ -73,6 +73,9 @@ set(IPEX_CPU_CPP_SRCS ${IPEX_CPU_CPP_DYNDISP_SRCS} ${IPEX_CPU_CPP_ISA_SRCS_GEN}
 
 list(REMOVE_ITEM IPEX_CPU_CPP_SRCS ${IPEX_CPU_CPP_ISA_SRCS_ORIGIN})
 
+# Disable XCR check to support Virtual Machines. Some hypervisor can't simulate XCR0 correctly.
+# add_definitions (-DENABLE_XCR_CHECK)
+
 add_library(${PLUGIN_NAME_CPU} SHARED ${IPEX_CPU_CPP_SRCS})
 
 set_target_properties(${PLUGIN_NAME_CPU} PROPERTIES ONEDNN_INCLUDE_DIR "${IPEX_CPU_CPP_THIRD_PARTY_ROOT}/ideep/mkl-dnn/include")

csrc/cpu/isa/cpu_feature.cpp

@@ -133,6 +133,7 @@ bool CPUFeature::os_avx() {
     return false;
   }
 
+#ifdef ENABLE_XCR_CHECK
   uint64_t xcrFeatureMask = 0;
   bool ret = read_xcr(_XCR_XFEATURE_ENABLED_MASK, &xcrFeatureMask);
   if (!ret) {
@@ -155,11 +156,12 @@ bool CPUFeature::os_avx() {
     Intel® Advanced Vector Extensions (AVX state). See Section 13.5.3
   */
   uint32_t avx_feature_bits = BIT_M_TO_N_64(xcrFeatureMask, 1, 2);
-  if (avx_feature_bits == 0b11) {
-    return true;
+  if (avx_feature_bits != 0b11) {
+    return false;
   }
+#endif
 
-  return false;
+  return true;
 }
 
 bool CPUFeature::os_avx2() {
@@ -182,6 +184,7 @@ bool CPUFeature::os_avx2() {
     return false;
   }
 
+#ifdef ENABLE_XCR_CHECK
   uint64_t xcrFeatureMask = 0;
   bool ret = read_xcr(_XCR_XFEATURE_ENABLED_MASK, &xcrFeatureMask);
   if (!ret) {
@@ -204,14 +207,16 @@ bool CPUFeature::os_avx2() {
     Intel® Advanced Vector Extensions (AVX state). See Section 13.5.3
   */
   uint32_t avx_feature_bits = BIT_M_TO_N_64(xcrFeatureMask, 1, 2);
-  if (avx_feature_bits == 0b11) {
-    return true;
+  if (avx_feature_bits != 0b11) {
+    return false;
   }
+#endif
 
-  return false;
+  return true;
 }
 
 bool CPUFeature::os_avx512() {
+#ifdef ENABLE_XCR_CHECK
   uint64_t xcrFeatureMask = 0;
   bool ret = read_xcr(_XCR_XFEATURE_ENABLED_MASK, &xcrFeatureMask);
   if (!ret) {
@@ -237,14 +242,16 @@ bool CPUFeature::os_avx512() {
   component 7 is used for the 16 512-bit registers ZMM16–ZMM31 (Hi16_ZMM state).
   */
   uint32_t avx512_feature_bits = BIT_M_TO_N_64(xcrFeatureMask, 5, 7);
-  if (avx512_feature_bits == 0b111) {
-    return true;
+  if (avx512_feature_bits != 0b111) {
+    return false;
   }
+#endif
 
-  return false;
+  return true;
 }
 
 bool CPUFeature::os_amx() {
+#ifdef ENABLE_XCR_CHECK
   uint64_t xcrFeatureMask = 0;
   bool ret = read_xcr(_XCR_XFEATURE_ENABLED_MASK, &xcrFeatureMask);
   if (!ret) {
@@ -275,11 +282,12 @@ bool CPUFeature::os_amx() {
   tile data (XTILEDATA state).
   */
   uint32_t avx512_feature_bits = BIT_M_TO_N_64(xcrFeatureMask, 17, 18);
-  if (avx512_feature_bits == 0b11) {
-    return true;
+  if (avx512_feature_bits != 0b11) {
+    return false;
   }
+#endif
 
-  return false;
+  return true;
 }
 
 #ifdef __linux__

tests/cpu/isa/CMakeLists.txt

@@ -11,4 +11,5 @@ set(IPEX_PROJECT_TOP_DIR "${PROJECT_SOURCE_DIR}/../../../")
 set(CPU_FEATURE_SRC "${IPEX_PROJECT_TOP_DIR}/csrc/cpu/isa/")
 
 add_definitions (-DCPU_FEATURE_EXEC)
+add_definitions (-DENABLE_XCR_CHECK)
 add_executable (cpu_features ${CPU_FEATURE_SRC}/cpu_feature.cpp ${CPU_FEATURE_SRC}/cpu_feature_main.cpp)