cl_mem_perf test cases failing

[monological]

I built and loaded a cl_mem_perf AFI onto an F2 FPGA instance and ran the test cases in the runtime directory. Only 3 out of the 5 pass. The test_dram_dma_* tests seem to be failing. I've attached the Vivado log for reference.

cl_mem_perf_2025_04_04-164043.vivado.log

ubuntu@ip~/src/project_data/aws-fpga/hdk/cl/examples/cl_mem_perf/software/runtime$ sudo ./test_aws_clk_gen
===================================================
Running test_aws_clk_gen
===================================================
slot_id     = 0
===================================================
__INFO__: deassert_clk_resets()
__INFO__: measure_clk_freq()
__INFO__: display_results()
__INFO__: REF_FREQ_CTR    = 100000000
__INFO__: clk_main_a0     = 250.0000 MHz
__INFO__: clk_extra_a1    = 125.0000 MHz
__INFO__: clk_extra_a2    = 375.0000 MHz
__INFO__: clk_extra_a3    = 500.0000 MHz
__INFO__: clk_extra_b0    = 450.0000 MHz
__INFO__: clk_extra_b1    = 225.0000 MHz
__INFO__: clk_extra_c0    = 300.0000 MHz
__INFO__: clk_extra_c1    = 400.0000 MHz
__INFO__: clk_hbm_axi     = 450.0000 MHz
__INFO__: clk_hbm_ref     = 100.0000 MHz
2025-04-04T21:04:31.462669Z, test_aws_clk_gen, INFO, test_aws_clk_gen.c +118: main(): TEST PASSED

ubuntu@ip:~/src/project_data/aws-fpga/hdk/cl/examples/cl_mem_perf/software/runtime$ sudo ./test_clk_freq
===================================================
Running test_clk_freq
===================================================
slot_id     = 0
===================================================
__INFO__: Dynamic config clk_extra_a1 = 87 MHz, clk_extra_b0 = 125 MHz, clk_extra_c0 = 250 MHz, clk_hbm_axi = 437 MHz
__INFO__: measure_clk_freq()
__INFO__: display_results()
__INFO__: REF_FREQ_CTR    = 100000000
__INFO__: clk_main_a0     = 250.0000 MHz
__INFO__: clk_extra_a1    = 87.5000 MHz
__INFO__: clk_extra_a2    = 58.3333 MHz
__INFO__: clk_extra_a3    = 58.3333 MHz
__INFO__: clk_extra_b0    = 125.0000 MHz
__INFO__: clk_extra_b1    = 79.1667 MHz
__INFO__: clk_extra_c0    = 250.0000 MHz
__INFO__: clk_extra_c1    = 79.1667 MHz
__INFO__: clk_hbm_axi     = 436.2500 MHz
__INFO__: clk_hbm_ref     = 100.0000 MHz
__INFO__: Resetting all MMCMs to default frequencies
__INFO__: measure_clk_freq()
__INFO__: display_results()
__INFO__: REF_FREQ_CTR    = 100000000
__INFO__: clk_main_a0     = 250.0000 MHz
__INFO__: clk_extra_a1    = 125.0000 MHz
__INFO__: clk_extra_a2    = 375.0000 MHz
__INFO__: clk_extra_a3    = 500.0000 MHz
__INFO__: clk_extra_b0    = 450.0000 MHz
__INFO__: clk_extra_b1    = 225.0000 MHz
__INFO__: clk_extra_c0    = 300.0000 MHz
__INFO__: clk_extra_c1    = 400.0000 MHz
__INFO__: clk_hbm_axi     = 450.0000 MHz
__INFO__: clk_hbm_ref     = 100.0000 MHz
2025-04-04T21:04:41.292202Z, test_clk_freq, INFO, test_clk_freq.c +138: main(): TEST PASSED

ubuntu@ip:~/src/project_data/aws-fpga/hdk/cl/examples/cl_mem_perf/software/runtime$ sudo ./test_dram_dma_hwsw_cosim
Memory has been allocated, initializing DMA and filling the buffer...
2025-04-04T21:04:48.435598Z, test_dram_dma_hwsw_cosim, ERROR, test_dram_dma_hwsw_cosim.c +164: dma_example_hwsw_cosim(): unable to open read dma queue
2025-04-04T21:04:48.435630Z, test_dram_dma_hwsw_cosim, ERROR, test_dram_dma_hwsw_cosim.c +116: main(): DMA example failed

ubuntu@ip:~/src/project_data/aws-fpga/hdk/cl/examples/cl_mem_perf/software/runtime$ sudo ./test_dram_dma_hwsw_cosim
Memory has been allocated, initializing DMA and filling the buffer...
2025-04-04T21:04:54.251514Z, test_dram_dma_hwsw_cosim, ERROR, test_dram_dma_hwsw_cosim.c +164: dma_example_hwsw_cosim(): unable to open read dma queue
2025-04-04T21:04:54.251555Z, test_dram_dma_hwsw_cosim, ERROR, test_dram_dma_hwsw_cosim.c +116: main(): DMA example failed

ubuntu@ip:~/src/project_data/aws-fpga/hdk/cl/examples/cl_mem_perf/software/runtime$ sudo ./test_hbm_perf32
===================================================
Running test_hbm_perf32
===================================================
slot_id     = 0
cfg_axlen   = 0x0000000f
cfg_wdata   = 0x12345678
cfg_wr_ctl  = 0xffffffff
cfg_rd_ctl  = 0xffffffff
cfg_runtime = 0x0000001e
===================================================
__INFO__: deassert_clk_resets()
__INFO__: initialize_hbm()
__INFO__: enable_hbm_kernl()
__INFO__: run_hbm_write_test() for 30s
__INFO__: run_hbm_read_test() for 30s
__INFO__: enable_hbm_kernl()
__INFO__: display_results()
__INFO__: -------------------------
__INFO__: Write Performance Results
__INFO__: -------------------------
__INFO__: calculate_perf()
__INFO__: WR CycCount     = 0x00000005eaaa4ae0
__INFO__: WR Timer        = 0x00000001bf095f26
__INFO__: WR Latency      = 160ns
__INFO__: WR Pending Txns = 0
__INFO__: WR RespError    = 0x00000000
__INFO__: WR Bandwidth    = 433.69 GBytes/s
__INFO__: -------------------------
__INFO__: Read Performance Results
__INFO__: -------------------------
__INFO__: calculate_perf()
__INFO__: RD CycCount     = 0x00000005d0340aec
__INFO__: RD Timer        = 0x00000001bf099512
__INFO__: RD Latency      = 272ns
__INFO__: RD Pending Txns = 0
__INFO__: RD RespError    = 0x00000000
__INFO__: RD Bandwidth    = 426.12 GBytes/s
2025-04-04T21:05:59.916139Z, test_hbm_perf32, INFO, test_hbm_perf32.c +157: main(): TEST PASSED

[czfpga]

@monological

Please refer to the Errata. Those failing tests use the XDMA engine to pass traffic and the XDMA shell is not available yet.

We'll enable the XDMA really soon. Please stay tuned. Thanks.