Development Board Based On The TMS320F28335 DSP For Applications of Power Electronics
Development Board Based On The TMS320F28335 DSP For Applications of Power Electronics
Development Board Based On The TMS320F28335 DSP For Applications of Power Electronics
Received: 11 Aug 2014 Accepted: 14 May 2015 Available Online: 29 May 2015
Abstract
This paper presents the design of a special purpose development board for power applications based on the digital signal
processor (DSP) TMS320F28335. We also propose some considerations for the design of any four-layer printed circuit
line with international recommendations to counteract the EMI (electromagnetic interference) and increase the EMC
(electromagnetic compatibility). Additionally, the main features of each module on the board and their respective
conditioning circuits designed are presented in order for the development board to be useful for any application of power
electronics as motor control, switching power supplies, LED lighting, communications through the electric network, etc.
Finally, a test protocol to verify the performance of the card and the comparison between the final cost per unit and similar
cards on the market were performed.
Key Words: anti-aliasing filter, electromagnetic interference, multilayer printed circuit board, signal conditioning,
sensitivity.
Resumen
En el presente artículo se presenta el diseño de una tarjeta de desarrollo de propósito específico en aplicaciones de potencia
con base en el procesador digital de señales (DSP) TMS320F28335. Se proponen además unas consideraciones para el
36 diseño de cualquier circuito impreso de cuatro capas acordes con las recomendaciones internacionales para contrarrestar
los efectos de interferencia electromagnética (EMI) y aumentar la compatibilidad electromagnética (EMC). Como factor
adicional se presentan las principales características de cada modulo en la placa y sus respetivos circuitos de
acondicionamiento, esto con el fin de que la placa de desarrollo sea útil para cualquier aplicación de electrónica potencia
como control de motores, fuentes conmutadas, iluminación LED, comunicaciones a través de la red eléctrica, etc. A
continuación, se realizó un protocolo de pruebas para verificar el funcionamiento de la tarjeta y la comparación entre el
costo final por unidad y las tarjetas similares presentes en el mercado. Finalmente, se presentan las conclusiones en donde
se resalta que la tarjeta implementada cumple con las características adecuadas para operar en el desarrollo de prototipos
electrónicos de potencia a nivel de innovación y/o investigación.
Palabras clave: Acondicionamiento de señales, circuito impreso multicapa, filtros antialiasing, interferencias
electromagnéticas, sensibilidad.
38
.
Figure 4 Adaptation Circuit of the Common Protocol - CAN.
Figure 5 Conditioning of the SPI standard.
The CAN protocol is based on the Carrier Sense Multiple of the filters and the space on the printed circuit board
Access model with a transmission rate up to 1 Mbps and a (PCB).
range of 40m. It discerns between temporary errors and Of the main topologies [7] [8], Sallen-Key Topology
permanent failures of nodes. It is adapted to the ISO 11898 (Figure 6 a) and Multi FeedBack (MFB) Topology
Standard by the IC SN65HVD232 CAN transceiver, as (Figure 6 b) both contain a single operational amplifier
shown in Figure 4 for a second order filter. Among these two, a sensitivity
analysis was performed [7], defined in Equation 1 where
The SCI is an asynchronous serial communication y represents parameters that mathematically model the
protocol with double buffer for transmission and reception filter and x represents the values of resistors and capacitors
functions. It is adapted to IC SN75179B differential driver conforming the filter, thus finding the topology
and receiver pair, and is ideal for applications with representing less percentage changes in the quality factor
balanced transmission lines in the RS-485 and RS-422 𝑄 and in the natural frequency of the filter 𝜔0 , according
standards. to the percentage changes in the market values of the
passive elements composing it. Topology to be selected
The ICC Module has a transmission rate of between 10 was based on the sensitivity calculations, the resistance for
kbps and 400 kbps. It is compatible with the frequencies and the lower value of the synthesis of the
Semiconductors IIC-bus v2.1 and is decoupled through sensitivities.
𝑦 𝜕𝑦 𝑥 (1)
the IC ADuM1250. 𝑆𝑥 =
𝜕𝑥 𝑦
2.5. PCB Design
The conditioning of the peripheral SPI was performed
through the integrated circuit ADuM1401 of four separate
and isolated channels, which are based on Analog Currently available technology has led to have circuits 39
Devices, Inc., iCoupler® technology, as seen in Figure 5. with a higher level of integration, considerably reducing
the sizes of the PCB and thus increasing the capacity of
This device is characterized by its low power consumption interfering one signal into another and, in general,
(a tenth of the conventional optocouplers, approximately) adverse electrical factors affecting signal integrity.
and ease of operation. It was created to be used in
applications with SPI interface for converting data with a
transmission rate up to 90 Mbps.
Linear polarization and analog and digital ground Avoid 90 degrees angles on paths carrying signals in
planes must be separated, as shown in Figure 7. high frequency band or higher, as these increases the
width of the track with a factor of 1.414, thus
Location of the parts having connections in common affecting the characteristic impedance at the corners
should be as close as possible and the copper traces of the paths. Thereby, changes in the trajectory
short and straight. In digital circuits, if the above greater than 45 degrees are not recommended.
condition cannot be met, parts that are functionally
related must kept close or the pieces with clock The use of decoupling capacitors helps filtrating the
signals at high frequencies and very short rising edges radiofrequency noise present in the signal power of
must be grouped. Thus, the size of the paths carrying integrated circuits. To use two or three different types
these signals can be minimized. of capacitors (tantalum, ceramic, electrolytic, etc.)
40 with values decline for decades from 0.1 nF is
In accordance with the IPC 2251, paths greater than recommended.
λ/15 length, must be designed according to the
transmission lines theory.
Figure 7 Separation of linear polarization and analog and digital ground planes.
3. Results
In accordance with the procedure described in section 2.4,
3.1. Topology definition for the antialiasing filter sensitivities shown in
Table 1 (were recommendation [9] was also followed to filter is given by (2) and whose denominator is a second
decrease sensitivity in the Sallen-Key topology regarding degree Bessel polynomial [20]. By matching this with the
passive elements), were obtained. The statements in this transfer functions of the topologies, statements contained
table are given by the combination of the nominal values in
of the passive elements, which in turn, are in function of Table 2 are generated.
the frequency response required to implement. Such
response is established towards minimizing the distortion 3𝜔𝑐2 (2)
in phase and magnitude to the signals to be sampled [16] 𝑠 2 + 3𝑠𝜔𝑐 + 3𝜔𝑐2
[17] [18] [19]
For such reason, frequency response of the Bessel type By replacing equations of
was selected, whose transfer function for a second order Table 2 in the statements of
Table 1, in Figure 8 are presented the behaviors for the topology, taking into account different orders of
Sallen-Key topology, whose sensitivities are independent magnitude of the product 𝐶1 𝑓𝑐 . (𝑓𝑐 is the cut-off frequency
of 𝑓𝑐 , and in Figure 9 the behaviors shown for the MFB of the filter).
𝑑𝑄 𝑅2 √𝑅1
𝑆𝑅𝑄2 = ∗ 2(𝑅1 + 𝑅2 ) 2
𝑑𝑅2 𝑄 𝑅 𝑅 𝑅 𝑅
4𝑅1 𝑅2 𝑅3 [√ 2 3 + √ 2 + √ 3 ]
𝑅1 𝑅3 𝑅2
𝑅3
2𝑅1 𝑅2 𝑅3 + 𝑅1 (𝑅3 − 𝑅2 ) + 𝑅2 2 𝑅3 2
2 2
𝑑𝑄 𝑅3 √𝑅1
𝑆𝑅𝑄3 = ∗ 2
𝑑𝑅3 𝑄 𝑅 𝑅 𝑅 𝑅
4𝑅1 𝑅2 𝑅3 [√ 2 3 + √ 2 + √ 3 ]
𝑅1 𝑅3 𝑅2
𝑑𝑄 𝑘 𝐶1 𝑅1
𝑆𝑘𝑄 = ∗
𝑑𝑘 𝑄 𝐶2 (𝑅1 + 𝑅2 )
41
𝜔 𝑑𝜔0 𝐶1 1 1
𝑆𝐶10 = ∗ − −
𝑑𝐶1 𝜔0 2 2
𝜔 𝑑𝜔0 𝐶2 1 1
𝑆𝐶20 = ∗ − −
𝑑𝐶2 𝜔0 2 2
𝜔 𝑑𝜔0 𝑅1 1
𝑆𝑅10 = ∗ − 0
𝑑𝑅1 𝜔0 2
𝜔 𝑑𝜔0 𝑅2 1 1
𝑆𝑅20 = ∗ − −
𝑑𝑅2 𝜔0 2 2
𝜔 𝑑𝜔0 𝑅3 1
𝑆𝑅30 = ∗ −
𝑑𝑅3 𝜔0 2
𝜔 𝑑𝜔0 𝑘
𝑆𝑘 0 = ∗ 0
𝑑𝑘 𝜔0
1 √3 1
R3 𝑅3 = (− √3 − 8𝜌 + ) 𝜌 = 𝐶2 /𝐶1
𝜌𝐶1 𝜔 12 4
𝑸 𝑸
Figure 8 (𝒂)𝑺𝑹𝒙 , (𝒃)𝑺𝒌 Sallen-Key Topology
42
𝑸 𝑸 𝑸
Figure 9 𝑺𝑹𝟏 , 𝑺𝑹𝟐 , 𝑺𝑹𝟑 Multi FeedBack Topology.
Figure 11 shows the transmission of the word Table 3 shows those commercially available boards,
“hexadecimal 7555”, along with a configuration mode of similar to the ones developed in this project. Even though
the clock signal (0,0), that is to say, the bit transmission is these are specific boards, do not include conditioning of
given by each rising edge without delay. MISO signal is their peripherals such as: different voltage levels for the
captured in channel 1 of the oscilloscope for which the PWM signals and specific purpose inputs/outputs, anti-
logic level at an idle state is high and a transmission rate aliasing filters and signal conditioning for the ADC
of 300 kbps. Channels 2 and 3 respectively record SS and module. Another factor to consider is the cost per unit, due
SCLK signals. to the 50% decrease compared with the cheapest board
registered on Table 3.
Table 3 Comparison of the most representative similar
boards on the market.
COST
BOARD MAIN FEATURES PER
UNIT
Based on the TMS320F28335
DSP, is specifically designed for
industrial automation. Includes
TI28335DSK-II LCD, two communication $ 950 000
terminals RS-232, SD card
interface, switches for interrupting
and Ethernet interface.
Figure 11 SPI Standard, configuration of the clock signal Its main processor is the
CPHASE =0, CPOL = 0. TMS320F28335 DSP. Includes 16
ADC channels for analog signals
ICETEK- $ 1 586
On the third test the ADC module was used, in which a F28335-A
with width from -5 V to 5 V. 88
000
sinusoidal input signal to the filter entrance was input/output of general purpose.
Four (4) audio interfaces and two
introduced with a frequency corresponding to the cutoff D/A0 converters. 43
frequency (600 Hz), with amplitude of 15 V (Figure 12, Motor Control
It provides hardware and software
Ch1). Channel 2 has the output signal of the filter with Development
for motor control, software for
amplitude 10 V. Subsequently, the test signal is attenuated for $ 1 746
using fuzzy logic and PID
TMS320F28335 100
10% and elevated to a DC level of 1.5 V, effectively eZdsp™ with
algorithms. It is built upon the
obtaining a signal amplitude of 1V and 1.5V above the TMS320F28335 processor.
Socket
reference of channel 3 (Ch3). Finally, the test signal is
digitized at a sampling rate of 735.3 ksps and transmitted
to the DAC module for its conversion to analog (channel 4. Conclusions
4, Ch4).
A development board for power electronics applications
based on the Texas Instrument TMS320F28335 DSP,
which meets the proper characteristics to developments of
prototype and research was designed and implemented. It
has the necessary circuitry for setting and conditioning of
different modules associated to the DSP (PWM, DAC,
ADC, SPI, I2C, CAN, SCI, eQEP, eCAP, GPIO)
assembled on a PCB, which was designed based on
recommendations made by international organizations and
scientific articles published in the IEEE to counter the
adverse effects of electromagnetic interference.
b
Figure 12 ADCIN0 Block -Filter- Conditioner- DAC
Acknowledgments [9] S. Muralikrishna y S. Sathyamurthy, «An overview of digital
circuit design and PCB design guidelines - An EMC perspective,»
de Electromagnetic Interference & Compatibility, 2008.
This paper is the result of the research project “Design and INCEMIC 2008. 10th International Conference on, Bangalore,
implementation of a development board with digital signal 2008.
processor and specific purpose in power electronics [10] N. L. Eastman, «Considerations for mixed analog/digital PCB
design,» de WESCON/96, Anaheim, 1996.
applications” (“Diseño e implementación de una tarjeta de
desarrollo con procesador digital de señales, de propósito [11] J. Jing y K. Lingwen, «Study of signal integrity for PCB level,»
de Electronic Packaging Technology & High Density Packaging
específico en aplicaciones de electrónica de potencia”) (ICEPT-HDP), 2010 11th International Conference on, Xi'an,
partially funded by the Research and Scientific 2010.
Development Center of the Universidad Distrital. [12] J. López Sánchez, F. A. Rojas S., C. L. Trujillo y J. Guacaneme
Moreno, «Recomendaciones para el diseño de circuitos impresos
de potencia,» Revista cientifica y tecnologica de la facultad de
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