Wafer-scale integration

This article is about the system of building very-large integrated circuit networks. For WaferScale Integration Inc. (Fremont, Calif.), a vendor of EPROM and programmable system-chips acquired by STM, see STMicroelectronics § WaferScale Integration Inc.

Wafer-scale integration (WSI) is a system of building very-large integrated circuit (commonly called a "chip") networks from an entire silicon wafer to produce a single "super-chip". Combining large size and reduced packaging, WSI was expected to lead to dramatically reduced costs for some systems, notably massively parallel supercomputers but is now being employed for deep learning. The name is taken from the term very-large-scale integration, the state of the art when WSI was being developed.

Overview

In the normal integrated circuit manufacturing process, a single large cylindrical crystal (boule) of silicon is produced and then cut into disks known as wafers. The wafers are then cleaned and polished in preparation for the fabrication process. A photographic process is used to pattern the surface where material ought to be deposited on top of the wafer and where not to. The desired material is deposited and the photographic mask is removed for the next layer. From then on the wafer is repeatedly processed in this fashion, putting on layer after layer of circuitry on the surface.

Multiple copies of these patterns are deposited on the wafer in a grid fashion across the surface of the wafer. After all the possible locations are patterned, the wafer surface appears like a sheet of graph paper, with grid lines delineating the individual chips. Each of these grid locations is tested for manufacturing defects by automated equipment. Those locations that are found to be defective are recorded and marked with a dot of paint (this process is referred to as "inking a die" and more modern wafer fabrication techniques no longer require physical markings to identify defective die). The wafer is then sawed apart to cut out the individual chips. Those defective chips are thrown away, or recycled, while the working chips are placed into packaging and re-tested for any damage that might occur during the packaging process.

Flaws on the surface of the wafers and problems during the layering/depositing process are impossible to avoid, and cause some of the individual chips to be defective. The revenue from the remaining working chips has to pay for the entire cost of the wafer and its processing, including those discarded defective chips. Thus, the higher number of working chips or higher yield, the lower the cost of each individual chip. In order to maximize yield one wants to make the chips as small as possible, so that a higher number of working chips can be obtained per wafer.

Lowering cost

The significant fraction of the cost of fabrication (typically 30%-50%) is related to testing and packaging the individual chips. Further cost is associated with connecting the chips into an integrated system (usually via a printed circuit board). Wafer-scale integration seeks to reduce this cost, as well as improve performance, by building larger chips in a single package – in principle, chips as large as a full wafer.

Of course this is not easy, since given the flaws on the wafers a single large design printed onto a wafer would almost always not work. It has been an ongoing goal to develop methods to handle faulty areas of the wafers through logic, as opposed to sawing them out of the wafer. Generally, this approach uses a grid pattern of sub-circuits and "rewires" around the damaged areas using appropriate logic. If the resulting wafer has enough working sub-circuits, it can be used despite faults.

Challenges

Most yield loss in chipmaking comes from defects in the transistor layers or in the high-density lower metal layers. Another approach – silicon-interconnect fabric (Si-IF) – has neither on the wafer. Si-IF puts only relatively low-density metal layers on the wafer, roughly the same density as the upper layers of a system on a chip, using the wafer only for interconnects between tightly-packed small bare chiplets. Si-IF-based processors and network switches have been studied.

Production attempts

Early WSI attempt by Trilogy Systems

Many companies attempted to develop WSI production systems in the 1970s and 1980s, but all failed. Texas Instruments and ITT Corporation both saw it as a way to develop complex pipelined microprocessors and re-enter a market where they were losing ground, but neither released any products.

Gene Amdahl also attempted to develop WSI as a method of making a supercomputer, starting Trilogy Systems in 1980 and garnering investments from Groupe Bull, Sperry Rand and Digital Equipment Corporation, who (along with others) provided an estimated $230 million in financing. The design called for a 2.5" square chip with 1200 pins on the bottom.

The effort was plagued by a series of disasters, including floods which delayed the construction of the plant and later ruined the clean-room interior. After burning through about 1⁄3 of the capital with nothing to show for it, Amdahl eventually declared the idea would only work with a 99.99% yield, which wouldn't happen for 100 years. He used Trilogy's remaining seed capital to buy Elxsi, a maker of superminicomputers, in 1985. The Trilogy efforts were eventually ended and "became" Elxsi.

In 1989 Anamartic developed a wafer stack memory based on the technology of Ivor Catt, but the company was unable to ensure a large enough supply of silicon wafers and folded in 1992.

Wafer-scale devices in production

Cerebras Systems processor

On August 19, 2019, American computer systems company Cerebras Systems presented their development progress of WSI for deep learning acceleration. Cerebras' Wafer-Scale Engine (WSE-1) chip is 46,225mm² (215mm × 215mm), around 56× larger than the largest GPU die. It is manufactured by TSMC using their 16nm process. The WSE-1 features 1.2 trillion transistors, 400,000 AI cores, 18GB of on-chip SRAM, 100Pbit/s on-wafer fabric bandwidth, and 1.2Pbit/s I/O off-wafer bandwidth. The price and clock rate have not been disclosed. In 2020, the company's product, the CS-1, was tested in computational fluid dynamics simulations. Compared to the Joule Supercomputer at NETL, the CS-1 was 200 times faster, while using much less power.

In April 2021, Cerebras announced the WSE-2, with twice the number of transistors and 100% claimed yield, which is achieved by designing a system in which any manufacturing defect can be bypassed. The Cerebras CS-2 system, which incorporates the WSE-2, is in serial production.

In March 2024, Cerebras announced the WSE-3 with twice the performance of the previous record-holder, the Cerebras WSE-2, at the same power draw and for the same price. It is aimed at AI training and built on TSMC's 5nm process.

See also

• Wafer-level packaging

External links

• "Giant microcircuits for superfast computers", Jim Schefter, Popular Science, January 1984, pp 66–67, 155