The Low Power GigaBit Transceiver (lpGBT) is a radiation-tolerant Application-Specific Integrated Circuit (ASIC) designed to implement versatile high-speed bi-directional serial links in the experiments and environment of the Large Hadron Collider. With 336 programmable registers and 11 configuration pins, this ASIC is highly configurable. The current version of the chip, the lpGBTv1, is now under test. The project will then produce chips to equip the phase-2 experiment upgrades starting in 2025. More than 180000 components will be produced, tested and distributed to the users. The test involves validation of a wide variety of features and will be achieved at three different supply voltages, at −30 °C and at room temperature. Given the number of components and the complexity of the test, one of the biggest challenges was to minimize the execution time while maximizing coverage. This paper presents the new lpGBTv1 production test system, its development stages and some of the challenges which were met during its implementation.