Paper

Upgrade of the ALICE inner tracking system: Construction and commissioning

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Published 9 July 2020 © 2020 IOP Publishing Ltd
, , Focus on New Frontiers in Physics - Selected Papers from ICNFP 2019 Focus on New Frontiers in Physics - Selected Papers from ICNFP 2019 Citation Alessandra Fantoni and on behalf of the ALICE collaboration 2020 Phys. Scr. 95 084011 DOI 10.1088/1402-4896/aba0f7

1402-4896/95/8/084011

Abstract

ALICE (A Large Ion Collider Experiment) is the CERN LHC experiment optimized for the study of the strongly interacting matter produced in heavy-ion collisions, in particular the characterization of the quark-gluon plasma. After the successful operation of the experiment during the first two runs of the LHC, the ALICE collaboration is currently working on a major upgrade of its detectors, to be installed during the 2019–2020 Long Shutdown (LS2). The main goal is to increase the readout capabilities and allow recording of Pb–Pb minimum bias events at rates in excess of 50 kHz, which is the expected Pb–Pb interaction rate at the LHC after LS2. One key part of the upgrade is the construction of a new Inner Tracking System (called ITS2) that will significantly improve the impact parameter resolution of the tracks, tracking efficiency, and readout capacity which enables precise measurements of low momentum charged particles. The ITS2 consists of seven approximately-cylindrical detector layers of CMOS Monolithic Active Pixel Sensors (MAPS) with the sensor matrix and readout integrated on a single chip, named ALPIDE (ALice PIxel DEtector), covering an area of 10 m2 and containing about 12.5 billion pixels. All layers are mounted on ultra-lightweight carbon support structures with an embedded cooling system. This allows a reduction of the material budgets down to about 0.3% X0 for the inner layers and 1% X0 for the outer layers, with respect to the previous ITS system. After a brief overview of the upgrade motivation, details of the overall layout will be given as well as the construction and commissioning status and plans.

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1. Introduction

The ALICE (A Large Ion Collider Experiment) [1] experiment is upgrading its apparatus during the currently ongoing Long Shutdown 2 (LS2) of the LHC at CERN in 2019–2020. During this time ALICE will replace the previous Inner Tracking System (ITS), based on silicon strip sensors, silicon drift sensors, and silicon hybrid pixel sensors, with a completely new detector called ITS2, based on the Monolithic Active Pixel Sensor (MAPS) technology. This upgrade is needed to provide a more precise and efficient vertex reconstruction, and low transverse momentum (pT) tracking. This is achieved through the reduction of the material budgets by a factor of four compared to the previous ITS, installation of a reduced diameter beam-pipe, allowing for the inner-most layer to be closer to the collision vertex, and also by providing a continuous readout to sample the full interaction rate.

ALICE will improve its sensitivity to rare probes by recording Pb–Pb collision data in a continuous readout mode at a 50 kHz interaction rate which is a factor of six higher than in LHC Run 2 after the accelerator upgrade. Furthermore, the vertexing performance will provide a more effective reconstruction of heavy-flavour hadron decays.

2. The new inner tracking system

The most relevant features of the new Inner Tracking System ITS2 are:

  • (a)  
    improvement of charged-particle track impact parameter resolution by a factor of three. This is achieved by: (1) reduction of the beryllium beampipe (0.8 mm thick) inner radius from 29 mm to 18.2 mm, allowing the first detector layer to be moved closer to the collision point; (2) reduction of material budget to minimize the multiple Coulomb scattering (the three inner layers have a radiation length of 0.35% X0/layer, compared with 1.14% X0/layer of the previous ITS); 3) reduction of pixel size from 50 × 425 μm2 to 29 × 27 μm2, achieving a spatial resolution of ∼5 μm;
  • (b)  
    improvement of tracking efficiency and pT resolution at low pT by increasing the granularity: seven layers of pixel sensors covering a radial extension from 22 to 400 mm, to be compared to the previous combination of six layers of pixel, drift and strip sensors, two layers each;
  • (c)  
    increased readout capabilities up to 100 kHz in Pb--Pb collisions and several 105 Hz for pp interactions, with respect to the limit of 1 kHz of the ITS in Run 1 and Run 2;
  • (d)  
    fast insertion/removal for yearly maintenance, with the possibility to replace non functional detector parts during the yearly LHC shutdown.

2.1. The ITS2 layout

The ITS2 will be the first large-area silicon tracker based on the CMOS MAPS technology operating at a collider facility.

The ITS2 layout is shown in figure 1. It includes seven coaxial cylindrical layers grouped into two sub-systems: the Inner Barrel (IB), consisting of three 27 cm-long layers with radii of 2.3, 3.1 and 3.9 cm, and the Outer Barrel (OB), composed of two 84 cm-long Middle Layers (ML) placed at 20 and 25 cm from the interaction line, and two 148 cm-long Outer Layers (OL) at 35 and 40 cm. The layers cover a total surface area of ∼10 m2 with 12.5 G pixels [2].

Figure 1. Refer to the following caption and surrounding text.

Figure 1. Schematic layout of the ITS2, with three inner layers close to the beam pipe, two middle layers and two outer layers. The full detector will have a radius of 405 mm and a length of 150 cm. Reproduced from [2]. © IOP Publishing Ltd. CC BY 3.0.

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The same silicon pixel sensor is used to equip all layers. The layers are segmented in the rϕ direction into elements called staves, which extend the full length of the detector in the direction of the beam.

A stave is composed of one or more Hybrid Integrated Circuit (HIC), depending on the layer, which are glued onto two (one) cold plates for the OB (IB) that are supported by a space frame. The HIC consists of a Flexible Printed Circuit board (FPC) and silicon pixel sensors which are electrically connected to it through wirebonds. The cold plate has a form of a carbon ply which is equipped with two cooling pipes.

Each stave of the IB consists of nine silicon pixel chips, that are mounted onto a shared FPC board, providing the power, control, clock, and data transmission for the devices. Each chip operates independently and has its own separate high-speed serial data output link operating at 1200 Mbps. The clock and control signals are commonly distributed to the nine sensors.

The OB uses modules consisting of two groups of sensors. In each group there is one chip assigned as the master chip and six chips that are slave chips. The master forwards the data from the six slaves over a 400 Mbps link, in addition it redistributes the clock and control signals to the slaves. Such a setup is suitable for the ITS2 OL and ML as the expected occupancies are much less then those of the IB, which is as close as 22 mm to the interaction point. In fact, the occupancies are 2.61 pixel/chip for the OL and 6.16 ÷ 8.87 pixel/chip for the ML, compared to 150 ÷ 316 pixel/chip for the IB (from the outer to the innermost layer) [3].

The staves of the MLs and OLs consist of 2 × 4 and 2 × 7 of HICs, respectively.

A schematic view of the IB and OB staves are shown in figure 2, respectively on the top and bottom panel.

Figure 2. Refer to the following caption and surrounding text.

Figure 2. Exploded schematic view of an IB stave (top) and an OB stave (bottom). Reproduced from [2]. © IOP Publishing Ltd. CC BY 3.0.

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The full ITS2 consists of 48 staves for the IB and 144 staves for the OB, of which 54 for the MLs and 90 for the OLs.

Table 1 presents the detector layers geometrical characteristics.

Table 1. ITS2 layout components.

BarrelLayersRadiusLength# of Staves#HIC /staveTotal # chips
  (mm)(mm)   
InnerLayer 022.4271121108
InnerLayer 130.1271161144
InnerLayer 237.8271201180
OuterLayer 3194.48432482688
OuterLayer 4243.98433083360
OuterLayer 5342.3147542148232
OuterLayer 6391.8147548149408

2.2. The ALPIDE pixel sensor

The ALICE physics program requires a new, fast, low material budget, and radiation tolerant silicon tracker. Because of this, the ITS2 utilizes a custom-designed silicon MAPS chip called ALPIDE (ALice PIxel DEtector) [48], developed within the ALICE Collaboration for this application. The chip has a size of 15 × 30 mm2 and has a matrix of 512 × 1024 pixels, each pixel spans of 29 × 27 μm2.

It is produced in the TowerJazz 180 nm CMOS imaging process, which provides a deep P-well that can be used to shield the N-well of PMOS transistors. This allows the use of full CMOS circuitry in the pixel area without the drawback of parasitic charge collection by the N-wells. This process allows the use of a high-resistive (>1 kΩ · cm) epitaxial layer on a p-substrate, which increases the radiation tolerance. In addition, a moderate negative voltage to the substrate can be applied to increase the depletion zone around the collection diode and improve the signal-to-noise ratio.

The main characteristics of the sensor are:

  • pixel size: 29 × 27 μm2;
  • thickness: 50 μm for the inner layers and 100 μm for the outer layers;
  • integration time: <20 μs;
  • in-pixel discriminators and in-matrix address encoder with asynchronous sparsified readout, so it can be operated in either triggered acquisition mode (200 kHz and 1 Mhz for Pb-Pb and pp collisions, respectively) or continuous acquisition mode;
  • high speed serial data output: up to 1.2 Gbit/s;
  • ultra-low power consumption: 40 mW cm−2;
  • detection efficiency: more than 99%;
  • spatial resolution: ∼5μm.

After successful laboratory tests at several institutes participating in the ALICE ITS upgrade project, the ALPIDE chips have been brought to a number of test beam facilities, namely DESY (5 GeV e in Hamburg-Germany), BTF (450 MeV e in Frascati-Italy), PAL (60 MeV e in Pohang-South Korea), PS (6 GeV π at CERN), and SPS (120 GeV π at CERN).

Results from test beams on the ALPIDE pixel chips are reported in [9]. No performance degradation has been observed up to a threshold of 200 e at integrated doses reaching the Technical Design Report radiation tolerance requirements of 2.7 Mrad total ionising doses and 2.7 × 1013 1 MeV neq cm−2 non-ionising energy loss, which is above the expectation of the lifetime of the detector.

2.3. Component and detector production

The electrical and functional tests of the ALPIDE chips have been performed at CERN for the 50 μm thinned chips and at Yonsei and Pusan/Inha (South Korea) for the 100 μm thinned chips.

From the end of 2016 until the end of 2019, a total of 72000 ALPIDE sensors have been produced and tested. The overall chip production yield amounts to 63.9%.

For the IB HICs, only the best category of chips has been used, which has a yield of 30.4%.

The full production of HICs and staves for the IB has been carried out at CERN and was concluded at mid 2019. A total of 95 staves, enough to build two copies of the three inner barrel layers, have been assembled with a yield of 73%.

The OB HICs have been produced in five sites: Bari in Italy, Liverpool in UK, Pusan/Inha in South Korea, Strasbourg in France and Wuhan in China. The FPCs have been prepared and tested in Catania and Trieste in Italy. The OB HIC production started in 2017 and lasted in just under two years, with a total number of 2679 assembled HICs, and a final detector-grade yield of 84%, leaving 564 working spare OB HICs on top of the 1692 units composing the OB layers.

After full validation is done through a series of functionality tests, the OB HICs were shipped to the OB stave construction sites: Berkeley in USA for the ML staves; Daresbury in the UK, Frascati and Torino in Italy, NIKHEF in the Netherlands for the OL staves.

With the use of a Coordinate Measuring Machine (CMM), a series of four (for the MLs) or seven (for the OLs) HICs were aligned and glued onto a carbon composite cold plate, which embeds polyamide cooling pipes. The HICs are electrically interconnected to each other by soldering conductive bridges on their short edges. An FPC extension is added to the first HIC in the stave to connect the full chain to the external readout and control systems.

Such a unit is called Half-Stave (HS). Two HSs are then aligned and glued with partial overlap onto a space frame of the corresponding length, in order to form a full OL stave. The cross-cables extending on the right and left sides of the corresponding HSs, are soldered to an aluminum-kapton power bus for power distribution. Full functionality tests have been performed throughout the construction procedure to monitor the quality of the produced devices and give immediate feedback in order to improve the assembly techniques. The material budget of each OB layer amounts to ∼1% radiation length. The OB stave is designed to be read out at 400 Mpbs.

The OB stave mass production started in March 2018 and ended in September 2019, with a short tail of spares production after. The final detector-grade yield was ∼90%, including the post-production rework of a few staves, initially presenting functional issues. A total number of 10 ML and 11 OL detector-grade spare staves have been produced, on top of the 54 ML and 90 OL staves needed for the detector assembly. All have been shipped to CERN and fully validated at the reception.

Full readout logic is implemented in the ALPIDE chip that sends the digitized and zero-suppressed detector cluster data to the off-detector electronics. A total of 192 FPGA-based readout units have been produced and validated in Austin in the USA, CERN, Bergen in Norway, NIKHEF and Padova in Italy. They control and monitor the sensors and their power supply modules, receive the trigger and detector control information, and deliver the sensor data to the counting room. A total of 142 boards made in Berkeley in the USA are needed to power the full detector, in order to provide analog and digital 1.8 V supplies to each HIC plus a negative voltage output for the reverse bias. Production and qualification of the full set of readout and power boards was completed.

All the components for the mechanical support structure have been produced and verified at Berkeley, CERN, Padova and St. Petersburg in Russia. A dry insertion test of a dummy version of IB and OB half-detector has been successfully carried out.

The production of the ITS2 support structures and services, including the readout electronics and the power system, has been completed and all the units have been delivered to CERN to be integrated with the detector. Other details on the HIC and component production can be found in [1015].

2.4. Layer assembly

During the second half of 2018 until autumn 2019, all seven detector layers have been assembled and installed in the half-barrels in a dedicated assembly clean room at CERN There, the staves have been mounted on the corresponding half-layer mechanical supports in order to build the 14 half-layers composing the ITS2 detector. The half-layers have been then progressively arranged together to form the two IB half-barrels and the two OB half-barrels. In figure 3 the assembly of the bottom half of the IB and of the top half of the OB are shown.

Figure 3. Refer to the following caption and surrounding text.

Figure 3. Assembly photo of the bottom half of the IB (top); assembly photo of the top half of the OB (bottom).

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Starting from summer 2019, the four units are being sequentially connected to the pre-tested cooling, readout, powering and control system elements, in order to validate the full detector chain and exercise the system.

3. Commissioning

All detector services including cooling plant, power distribution, readout electronics, and computing systems have been installed in and around the assembly clean room to allow the full commissioning of the detector on surface.

Detector Control System and Data Acquisition System softwares are available and running on machines housed in a control room adjacent to the clean room.

A comprehensive commissioning, including cosmic muon data taking, is in progress. The commissioning shifts have been running since May 2019. The goal of these shifts is to control behavior of the main system and its components by monitoring the voltages, currents and temperatures of the detector, optimize the threshold setting, study the noise performance and verify the long-term stability of these parameters.

The final phase of installation in the ALICE cavern will start in summer 2020 and will be followed by integration in the ALICE central systems and global commissioning.

4. Detector performance

Starting from June 2019, acquisition of the first data using the staves in the first available half-layer, IB-HL0 (innermost layer of the IB), began. Threshold, DAC tuning, and noise occupancy scans are periodically performed to monitor the performance of the detector.

As already mentioned, the ALPIDE sensor must fulfill quite stringent requirements in terms of the fake-hit rate (to be less than 10−6/pixel/event). The threshold value for charge detection in pixel has been thus chosen as a trade-off between the detection efficiency and fake-hit rate. It was tuned to be lower than the expected charge produced by MIP, but at the same time, it was set high enough to suppress noise.

Results from the ITS2 IB commissioning are reported in figures 4 and 5. In figure 4 a fake-hit rate of 10−10 hits/pixel/event for the half-layer 0 of the IB is shown. This has been achieved by masking less than 50 pixels out of 28 millions pixels, which represents an excellent noise figure. This value is significantly better than the required 10–6 fake hits per pixel and event requested. One example of the threshold map obtained after the tuning of the relevant DAC parameters and the effect of this tuning on the threshold distribution is visible in figure 5 for all three half-layers of the IB top. Here, a nearly uniform level of the threshold after the tuning for all the chips belonging to the IB is visible. The overall uniformity is excellent and the tuning procedure has been validated.

Figure 4. Refer to the following caption and surrounding text.

Figure 4. The distribution of fake-hit rate of 54 chips in the half-layer normalized per pixel and per event as a function of the number of masked pixels. Pixels were divided into several groups according to frequency with which they fired and these groups are shown in different colors. The legend quotes for each group how many times have pixels belonging to this group fired in 15M events. Mean threshold after tuning is 100 e.

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Figure 5. Refer to the following caption and surrounding text.

Figure 5. The threshold map values for all the pixels in the staves included in one IB half-barrel, after tuning of the DAC parameters. The value of threshold is in DAC units where 10 DAC counts correspond to 100 e. The black values give an average threshold calculated for each sensor.

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Cosmic runs are routinely taken to validate the intrinsic alignment of the detector. During the ongoing commissioning the reconstruction of cosmic rays tracks was performed initially using a single IB half layer, and later using an IB half-barrel. Figure 6 shows a detector sketch to demonstrate how the track reconstruction is possible using a single half-layer.

Figure 6. Refer to the following caption and surrounding text.

Figure 6. Track reconstruction procedure for the first cosmic ray identified in the half-layer 0 of the IB, including cluster shape of the track hit in the three crossed staves.

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It is also interesting to notice how the shape of the pixel cluster associated to the hit changes in the staves that are sequentially crossed: in the first stave (number 6), where the particle crossing is almost perpendicular to the sensor surface, the cluster is small; in the second and third staves (numbers 7 and 8, respectively), where the angle between the track and the chip plane decreases, the cluster becomes large and starts to resemble a segment of track.

Figure 7 shows an artistic view of tracks reconstructed in the whole half-layer top of the IB produced by many overlapped events.

Figure 7. Refer to the following caption and surrounding text.

Figure 7. Example of reconstructed cosmic ray tracks from may overlapped events using one half layer of the IB.

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From July 2019 the full detector is kept powered and running; continuous monitoring is provided by three shift crews alternating within a 24 h, 7 days per week. Software development and hardware integration proceed in parallel, in addition the preparation of all the infrastructures in the experimental area for the final installation.

5. Summary and outlook

The major upgrade of the new ALICE ITS is being carried out to meet the challenges of the physics program of the ALICE experiment after the LHC LS2. Currently, the ITS upgrade is entering its final phase, which means preparation for installation into the ALICE detector, which is done in parallel with the on-surface commissioning. The installation of the new detector inside the experimental area is scheduled to start during summer 2020. Presently, the ITS2 represents the first large scale application of MAPS.

The first results of performance of the detector assemblies show very good agreement with targeted values and meet all requirements for the future ALICE physics program during Run 3 and Run 4 of the LHC.

The practical know-how, as well as the related physics analysis, will open new perspectives in view of the new generation of many different high performance silicon detectors as well as in frontier precision for high energy experiments. In addition, this project will open a range of new opportunities for applications that benefit from a high resolution tracking system, able to operate in vacuum and within a magnetic field, and in many other environments, including the use of hadrons (mainly protons and carbon ions) for cancer radiation treatment.

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10.1088/1402-4896/aba0f7