Authors:
Mohammed Bakiri
1
;
Jean-François Couchot
2
and
Christophe Guyeux
2
Affiliations:
1
FEMTO-ST Institute, UMR 6174 CNRS, Université of Bourgogne Franche, Centre de Développement des Technologies Avancées and ASM-IPLS Team, France
;
2
FEMTO-ST Institute, UMR 6174 CNRS and Université of Bourgogne Franche, France
Keyword(s):
Random Number Generators, Chaotic Circuits, Discrete Dynamical Systems, Statistical Tests, Cryptography Hardware and Implementation, Applied Cryptography, FPGA.
Related
Ontology
Subjects/Areas/Topics:
Applied Cryptography
;
Cryptographic Techniques and Key Management
;
Data and Application Security and Privacy
;
Data Engineering
;
Databases and Data Security
;
Information and Systems Security
;
Network Security
;
Privacy
;
Security and Privacy in Pervasive/Ubiquitous Computing
;
Security in Information Systems
;
Security Information Systems Architecture and Design and Security Patterns
;
Security Requirements
;
Software Security
;
Ubiquitous Computing Security
Abstract:
Sub-categories of mathematical topology, like the mathematical theory of chaos, offer interesting applications devoted to information security. In this research work, we have introduced a new chaos-based pseudorandom number generator implemented in FPGA, which is mainly based on the deletion of a Hamilton cycle within the n-cube (or on the vectorial negation), plus one single permutation. By doing so, we produce a kind of post-treatment on hardware pseudorandom generators, but the obtained generator has usually a better statistical profile than its input, while running at a similar speed. We tested 6 combinations of Boolean functions and strategies that all achieve to pass the most stringent TestU01 battery of tests. This generation can reach a throughput/latency ratio equal to 6.7 Gbps, being thus the second fastest FPGA generator that can pass TestU01.