Record link: 
http://hdl.handle.net/20.500.12708/15506
https://doi.org/10.34727/2020/isbn.978-3-85448-042-6_10
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Title: 
Runtime Verification on FPGAs with LTLf Specifications
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Citation: 
Tracy II, T., Tabajara, L., Vardi, M., & Skadron, K. (2020). Runtime Verification on FPGAs with LTLf Specifications. In A. Ivrii & O. Strichman (Eds.), Proceedings of the 20th Conference on Formal Methods in Computer-Aided Design – FMCAD 2020 (pp. 36–46). TU Wien Academic Press. https://doi.org/10.34727/2020/isbn.978-3-85448-042-6_10
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reposiTUm DOI: 
10.34727/2020/isbn.978-3-85448-042-6_10
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CatalogPlus: 
AC17202565
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Publication Type: 
Inproceedings - Full-Paper Contribution
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Language: 
English
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Authors: 
Tracy II, Tommy 
Tabajara, Lucas 
Vardi, Moshe 
Skadron, Kevin 
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Editors: 
Ivrii, Alexander 
Strichman, Ofer 
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Organisational Unit: 
E192-04 - Forschungsbereich Formal Methods in Systems Engineering 
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Series: 
Conference Series: Formal Methods in Computer-Aided Design 
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Published in: 
Proceedings of the 20th Conference on Formal Methods in Computer-Aided Design – FMCAD 2020 
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Volume: 
1
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Date (published): 
2020
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Number of Pages: 
11
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Publisher: 
TU Wien Academic Press, Wien
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Keywords: 
computer-aided system design
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Linked records in reposiTUm: is part of: 
10.34727/2020/isbn.978-3-85448-042-6
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License: 
CC BY 4.0 CC BY 4.0
en
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