Ultra-High-Speed Image Signal Accumulation Sensor
Abstract
:1. Introduction
2. ISAS Structure Utilizing a Two-Phase Transfer System
2.1. Structure of the ISAS
- One CCD element consists of a channel element under a couple of alternately placed electrodes A1 and A2.
- Under each electrode, built-in potential barriers are alternately placed on the upper and the lower halves of the neighboring CCD channels.
- At each fold, a barrier is placed on the left half of the horizontally connecting CCD part to transfer the signal charge packet horizontally.
2.2. Simulation Result at a Fold of the Folded CCD Storage
3. ISAS Structure Utilizing a Four-Phase Transfer System
3.1. Structure
3.2. Gates and Their Basic Operations
3.3. Operation Modes of CCD-ISAS
3.4. Simulation Result at a Fold of the Folded CCD Storage
3.5. Frame Rate Limitation of the ISAS
- Employ a BSI (Backside Illumination) structure, and
- Place crossed differential buslines on the top of the front surface by using a couple of additional metal layers.
3.6. Expected Noise Performance
3.7. Hybrid CCD/CMOS-ISAS
4. Potential Applications
- The target event is reproducible.
- Light intensity is low which generates a signal electron packet much less than the full well capacity of a single storage element
- Number of frames required is up to 100 to 200 frames.
5. Conclusions
- A fold of a CCD with a simple and practical configuration.
- Connection of the first and the last elements of a topologically linear CCD.
References and Notes
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Appendix 1
Appendix 2
- One CCD element of the four-phase system consists of a channel element with four driving electrodes. Therefore, if the size of the CCD element is the same, the width of the electrode is a half of that for the two-phase system, which requires a much finer fabrication process and causes lower DC-yield.
- The transfer speed of the four-phase transfer is a half or a quarter of that of the two-phase transfer.
- The charge handling capacity of the four-phase transfer is three to six times larger than that of the two-phase transfer.
- The four-phase transfer is much more stable than the two-phase transfer. Design of image sensors with the four-phase transfer is much easier.
Appendix 3
Appendix 4
- CL (collection gate): to collect photo-electrons generated from the backside of each pixel to the in situ storage on the front side.
- IN (input gate): to transfer signal charge packets to first element of the in situ storage.
- AB (anti-blooming gate): to drain excessive charges out of the sensor.
- DR (drain): n-substrate contact.
- A1/A2: two-phase transfer electrodes for the in situ storage.
- A1/B2: two-phase transfer electrodes for the readout VCCD.
- A1/A2/A3/A4: four-phase transfer electrodes for the in situ storage.
- A1/B2/A3/B4: four-phase transfer electrodes for the readout VCCD.
- OW (over-writing gate): to help to drain charge packets out of the sensor.
- SW (switching gate): to transfer image signals stored in the in situ storage to readout VCCD.
- PWC (p-well contact): to drain holes generated in the front side out of the sensor.
- RG (reset gate): to control reset operation.
- FD: floating diffusion node.
- RC (readout circuitry): conventional CMOS readout circuitry consisting of one source follower transistor, and row and/or column select transistor(s).
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Etoh, T.G.; Son, D.V.T.; Akino, T.K.; Akino, T.; Nishi, K.; Kureta, M.; Arai, M. Ultra-High-Speed Image Signal Accumulation Sensor. Sensors 2010, 10, 4100-4113. https://doi.org/10.3390/s100404100
Etoh TG, Son DVT, Akino TK, Akino T, Nishi K, Kureta M, Arai M. Ultra-High-Speed Image Signal Accumulation Sensor. Sensors. 2010; 10(4):4100-4113. https://doi.org/10.3390/s100404100
Chicago/Turabian StyleEtoh, Takeharu Goji, Dao Vu Truong Son, Toshiaki Koike Akino, Toshiro Akino, Kenji Nishi, Masatoshi Kureta, and Masatoshi Arai. 2010. "Ultra-High-Speed Image Signal Accumulation Sensor" Sensors 10, no. 4: 4100-4113. https://doi.org/10.3390/s100404100