In this letter, a combinational logic reduced belief propagation (BP) decoder for polar codes is designed in 55 nm CMOS technology. The authors first introduced the BP decoding algorithm for polar codes, and then analyzed the architectures of the conventional BP decoders. Finally, the hardware implementation with the proposed multiplexed process element architecture is presented. Synthesis results show that the consumption of hardware resources is reduced by 36%. The architecture and circuit techniques reduce the power to 398 mW for an energy efficiency of 292 pJ/b. The throughput is improved to 4.36 Gbps by applying the G-matrix early stopping criteria.