Diffusive and ballistic transport in thin InSb nanowire devices using a few-layer-graphene-AlO_x gate

Improving the electronic cleanliness of quantum devices based on low-dimensional semiconductors, such as nanowires (NWs) or quantum wells, is of paramount importance for creating robust and tunable quantum states and for enabling quantum technologies. InSb and InAs NWs have a wide range of desirable properties, including strong spin-orbit coupling (SOC) [1] and large g-factors [2, 3], that make their use appealing for realizing qubits based on Majorana zero modes (MZMs) [4–7] and electrically-controlled spin-based qubits [8–10]. MZMs, which could be used to develop topologically-protected qubits, require proximitizing of NW with a conventional superconductor, such as Al. A key precursor of MZMs is the spin-helical state, in which momentum and spin become correlated. This arises in the normal state, without superconductors, and requires SOC and robust ballistic transport. However, establishing clean ballistic transport and the presence of the helical state have been sidestepped in most recent experiments on MZMs, which have prioritized more complex devices involving superconductors even when these underlying requirements were not reliably confirmed.

Recent theoretical analysis [11, 12] suggests that disorder, due to inhomogeneous dielectric environments, surface charges on the NW and impurities in the crystal lattice that occur during the growth process, is a key factor in determining whether the topological regime of MZMs can be reliably achieved.

The presence of quantized conductance is a clear indication of whether a NW device is sufficiently clean to host helical states and hence, potentially, MZMs, making investigations of quantized transport a critical first step towards ascertaining that MZMs can be realized using a given type of NW and nanofabrication process. Therefore, optimizing the materials and nanofabrication is an important task that is necessary in order to align the quality of quantum devices with the requirements of MZMs.

Past progress in stemless InSb NW growth has produced high-quality wires with a typical diameter of 90–120 nm [13]. Reducing the diameter of the wire and optimizing the dielectric environment that is used to tune the wire may elicit new phenomena by further enhancing quantum confinement, leading to larger inter-subband energy splitting and potentially reduced scattering in the relevant regime of few occupied transverse quantum modes.

Recent advances in the development of 2D materials offer new ways to electrostatically gate quantum devices by taking advantage of the low surface roughness and flexibility in stacking 2D materials. Owing to its high electrical conductivity, graphene has emerged as a widely studied material for the development of new, high-performance nanoelectronics devices such as sensors and transistors [14, 15]. However, because monolayer graphene is a Dirac semimetal [16], external gating is required to achieve a 'metallic' electrical conductivity [17]. In addition, the surface of graphene is chemically inactive [18], which inhibits the growth of thin dielectrics using conventional techniques such as physical vapor deposition and atomic layer deposition (ALD), thus restricting the usefulness of graphene as an electrostatic gate for tuning quantum devices. A possible solution for the issues above is using a graphene multilayer, since it is intrinsically metallic and has a more chemically active surface.

In this work, we demonstrate the structural and electrical characterization of thin ∼10 μm long InSb NW with a diameter of ∼55 nm. To optimize the dielectric environment surrounding the wire we developed a facile fabrication technique based on few-layer-graphene (FLG) and ALD-grown AlO_x to electrostatically gate the NW.

We fabricated stemless InSb NWs by following previously used techniques [19], where an InSb(111)B substrate with SiN_x mask is used. However, differing from previously reported InSb NWs, the holes in the mask are created with reactive ion etching (RIE) (Oxford Plasmalab System 100) as opposed to wet chemical etching methods. The nanoholes in the mask are filled with gold droplets, allowing for growth using a metalorganic vapor-phase epitaxy technique. Precursors of trimethylindium and trimethylantimony are used, where under high temperatures the organo-indium and organo-antimony bonds are broken, allowing the indium and antimony to interact with the gold droplet. The gold acts as the catalyst particle for the vapor-liquid-solid (VLS) method [20].

The fabrication of the FLG-AlO_x back gate begins with transferring FLG to a pre-patterned chip with gold electrodes. FLG was exfoliated from highly oriented pyrolytic graphite (HQ Graphene) and positioned deterministically using a transfer station. The FLG flake is placed on a SiO₂ substrate and partially overlaps with a gold electrode to connect the FLG to the voltage source.

The typical areas of the FLG flakes were selected to be larger than 50 μm² to have sufficient overlap with the gold electrode and to contain the entire length of the wire. A ∼55 nm layer of AlO_x was deposited on the entire chip using plasma enhanced ALD (PE-ALD, Fiji 2, Ultratech) at 150 °C. Although the FLG surface is more reactive than monolayer graphene it still lacks dangling bonds to react with the precursor using only thermal treatment, which causes the dielectric to grow with pinholes. Therefore, additional surface treatment is necessary to create nucleation sites for the precursor [21, 22]. The PE-ALD allows for the deposition of a dielectric layer on the FLG without pretreatment because it creates local defects using plasma that serves as nucleation site for the precursor.

To investigate the electrical properties of the NWs we used a mechanical transfer station with a micromanipulator and an optical microscope to position the NWs on the FLG-AlO_x back gates, then patterned leads using conventional electron-beam lithography. The NW is coated with a layer of native oxide; therefore, to make contact to the wire it is necessary to remove the oxide before putting on the metallic leads. The native oxide was removed using Ar ion milling, followed by in-situ evaporation of 10 nm of Ti and 140 nm of Au. The devices were pumped overnight and measured in a dilution refrigerator at measured temperature of ∼10 mK (unless indicated otherwise).

After the device has been electrically characterized, a transmission electron microscopy (TEM) lamella is prepared using a FEI Nova Nanolab 600i. Protective layers of carbon and platinum are deposited with an electron beam in vacuum. A lamella is cut using a gallium focused ion beam (FIB) and transferred to a half-moon TEM grid. The lamella is thinned by FIB milling in steps at 30 kV, 16 kV and finally 5 kV, which creates a window thinner than 100 nm. This window is subsequently studied with TEM, a probe-corrected JEOL ARM 200 F.

The first goal is to fabricate long and thin InSb wires and observe how the size of the mask opening influences the resulting wire diameter, as previously done [19]. The challenge is to create small, but well-defined, holes. Here, we found that RIE provides finer control of the dimensions of the opening in the mask than wet chemical etching (supplementary information, SI 1 and SI 4). By carefully tuning the growth temperature and incoming material flux (supplementary, SI 2 and SI 3), the dimensions of the wire are optimized while retaining a high yield. At sufficiently low overall flux the radial growth rate is 6× lower than the axial growth rate as a function of time (supplementary, SI 3), resulting in high aspect ratio NW.

This can be understood by the fact that radial growth is driven by a vapor–solid (VS) mechanism, and axial growth by the VLS mechanism in which growth is catalyzed by the Au particle. By optimizing growth parameters, a yield of $90 + \%$ has been obtained, with widths in the range 50–60 nm and lengths of 14 + μm (figures 1(a) and (b)). All NW exhibit the zincblende crystal structure and are free of stacking faults, as evidenced from side-view TEM inspection (supplementary, SI 7).

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Figure 1(c) shows a false color SEM image of a typical NW-on-FLG-AlOx back gate device. The blue area is the location of the deposited FLG. The entire chip is conformally coated with AlO_x . The electrodes were placed on top of the thin InSb NW, shown in gold and green respectively. The surface underneath the NW, FLG coated with AlO_x , appears to be much smoother than the Ti/Au leads. AFM measurements confirm that the surface of the FLG-AlO_x is significantly smoother compared to the Ti/Au-AlO_x (measured on the Ti/Au electrodes) with typical roughness of ∼170 ± 70 pm and ∼860 ± 70 pm respectively (supplementary, SI 8).

The cross-sectional TEM image (figure 1(d)) shows a cut of the measured NW device reported in all of the measured data and was performed subsequent to the transport measurements. The wire has a hexagonal shape and a corner to corner width of ∼55 nm. The wire is capped with ∼3 nm oxide due to self-terminating oxidation at ambient conditions and no process-induced crystal defects have been observed in the wire. In addition, the TEM cross-section of the FLG-AlO_x back gate revealed that the thickness of the FLG is ∼4.5 nm (supplementary, SI 6).

Because the NWs are very long, we are able to fabricate multiple devices on the same NW. In particular, we fabricated on the same NW a 'long' device with source-drain spacing ${d_{{\text{sd}}}} \approx$ 6 μm much larger than the mean-free-path (${l_{\text{s}}}\sim$300 nm) and a 'short' device with ${d_{{\text{sd}}}}$ ∼200 nm, on the order of ${l_{\text{s}}}$. The long device provides insight into diffusive transport, while the short device gives insight into quasi-ballistic transport.

The inset to figure 1(c) shows a conductance plot as a function of gate voltage (V_g) of the thin NW device with contact spacing of ∼6 μm. The conductance increases as a function of gate voltage up to the point of saturation at $\sim0.3\,{G_0},$ where ${G_0} = \frac{{2{e^2}}}{h}$. Measuring the pinch-off and conductance of the thin NW with contact spacing of ∼6 μm allows us to extract the field-effect mobility value, which is a property of the diffusive transport regime.

To extract the field-effect mobility, $\mu$, from this pinch-off data we treat the wire as a variable-conductance channel coupled to the gate electrode with a capacitance $C$. Additionally, we consider this channel in series with a fixed resistance ${R_{\text{S}}}$, which includes the contact resistance of the normal metal/wire interfaces, as well as the resistance of the fridge lines, filters, and measurement apparatuses. Together, this gives the gate-dependent conductance of the device as,

$$\begin{align}G\left( {{V_{\text{g}}}} \right) = {\left( {{R_{\text{S}}} + \frac{{{L^2}}}{{\mu C\left( {{V_{\text{g}}} - {V_{{\text{th}}}}} \right)}}} \right)^{ - 1}}\end{align} \tag{ 1 }$$

where L is the channel length and ${V_{{\text{th}}}}$ is the threshold gate voltage at which the Fermi level enters the conduction band and the device becomes conductive [13].

In order to fit this equation to our data, we calculate the capacitance between our gate and wire, using a self-consistent, finite-element Schrödinger–Poisson solver to simulate the exact geometry of our device, as described in [23]. For the thin $6\,\mu {\text{m}}$ long channel, we calculate this capacitance to be ∼600 aF. Fitting the data in figure 1(c) using this capacitance, we find our mobility to be μ= 12 700 ± 300 cm² Vs⁻¹.

Figure 2(a) shows the differential conductance (${\text{d}}I/{\text{d}}V)$ map as a function of gate voltage $({V_{\text{g}}})$ of the short device. The conductance map as a function of ${V_g}$ shows quasi-periodic diamond shape patterns. A series of line cuts taken from the conductance map (figure 2(a)) for −1.95 < V_sd < 1.95 mV as a function of ${V_g}$ )shown in figure 2(b)) show that the oscillations persist over a substantial range of gate voltages.

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The appearance of the diamond shape pattern indicates that the device acts as a Fabry−Peérot (FP) interferometer, a partially transmitting cavity for electron waves. The reflection may occur in part as a result of band bending near the contacts, as expected for a metal-semiconductor interface, and was observed before in InSb and InAs NW [24–26]. In addition, metallic contacts screen the electric field, such that the back gate tunability of the channel close to the contacts is reduced, resulting in different electron densities there vs. the central region between the contacts. As a result of these barriers, electrons experience multiple partial reflections near the contacts while propagating phase-coherently, which gives rise to FP interference, see supplementary, SI 9, for additional information. Setting a lower bound of $200\,{\text{nm}}$ (the contact spacing) for the length over which phase-coherent and quasi-ballistic transport can be achieved in these devices. The FP oscillations are very well-defined, with a large relative conductance modulation suggestive of transport that is close to the 1D limit. Although they reveal phase-coherent transport, FP oscillations may obscure other quantum phenomena, in particular quantized conductance plateaus associated with individual transverse quantum modes.

Applying an external magnetic field to the thin NW may cause suppression of FP oscillation by inducing dephasing between multiple trajectories. To investigate the presence of conductance plateaus, we apply an out-of-plane magnetic field $($ B = 2.8 T$)$ to suppress the FP oscillations (figure 3). Figure 3(b) shows a series of line cuts taken at −2 < V_sd< 2 mV from the differential conductance map, confirming that the FP oscillations are substantially reduced with respect to the B = 0 data. The line cuts reveal a conductance plateau that remains close to ${G_0}$ over a wide range of source-drain bias values, consistent with quantized transport superimposed with some residual oscillations due to FP interference.

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In addition, further plateau-like features appear, near $0.8\,{G_0}$ and $1.5\,{G_0}$, possibly related to Zeeman-split subbands (expected at odd multiples of $0.5\,{G_0}$) combined with conductance oscillations. At more positive gate voltages, strong conductance oscillations, consistent with FP interference, prevent the observation of any other plateaus. However, for MZM experiments, access to the lowest one or two subbands is generally sufficient.

To further investigate the robustness of the observed $1\,{G_0}$ plateau, we measure conductance at a higher temperature, which is expected to reduce the phase coherence and thus further suppress resonances such as those due to FP interference. Figure 4(a) shows a differential conductance map as function of V_g and ${V_{{\text{sd}}}}$ taken at 400 mK and B = 0. Note that the pinch-off voltage increased to V_g ∼ 3 V after the temperature change, possibly due to a spontaneous charge switch in the dielectric environment, either in the native oxide shell surrounding the wire or the ALD deposited gate dielectric. The finer oscillatory features seen at 10 mK in figure 2(a) are suppressed at 400 mK, however clear FP interference is still present, as evidenced by the multiple diamonds in the differential conductance map. Figure 4(b) shows a series of line cuts for −1.5 < V_sd < 1.5 mV. The oscillations appear to contain fewer harmonic components than in the 10 mK data, consistent with suppression of phase coherence and hence interference between fewer coherent trajectories. For 3.2 < V_g < 3.8 V the conductance values again coalesce near the value of $1\,{G_0}$, providing further evidence that this plateau feature is likely due to the lowest transverse subband in the NW.

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To gain better understanding of the origin of the FP oscillations and their interplay with subband quantization, we performed tight-binding numerical simulations using the KWANT [27] Python software package. We show that one possible origin of FP oscillations in our system is the difference in the chemical potential between the metallic leads and the semiconducting NW. The Hamiltonian of our NW is defined as:

$$\begin{align}H = \left( {\frac{{{p^2}}}{{2{m^*}}} - \mu } \right) - i{\alpha _R}{\sigma _z}\frac{\partial }{{\partial x}}.\end{align} \tag{ 2 }$$

The first term of the Hamiltonian is the kinetic energy and the second term of the Hamiltonian describes the Rashba SOC, where ${\alpha _R}$ is the Rashba spin-orbit coefficient and ${\sigma _z}$ is the z-component of the Pauli matrix. We ignore the Zeeman coupling as we only consider the case with applied field $\vec B = 0$. We simulate this by discretizing $H$ over a square mesh with a lattice constant $a$ = 5 nm. The width of NW is set to $60\,{\text{nm}}$ with a contact spacing of 200 nm [28]. The Hamiltonian of the leads includes only the kinetic energy term from the above-defined $H$. In the discretized model for simplicity, we work in units where the hopping energy term $t = \frac{\hbar }{{2{m^{{*}}}{a^2}}}$, and we set the Rashba spin-orbit term to be $\frac{{{\alpha _R}}}{a} = 0.9t$.

Figure 5(a) shows the subbands for a one-dimensional semiconductor with SOC and Zeeman coupling. The subbands are shifted relative to each other along the k-axis due to the SOC. The red curve in figure 5(b) shows conductance as a function of the energy of the incident electrons through this system. This is valid under the assumption that there is no chemical potential difference between leads and the wire and we obtain clean quantized conductance plateaus. However, this does not represent a typical NW experiment because the chemical potential of the NW is tuned by applying an electric field using a gate, and the field in the leads area is screened by the metallic contacts. This gives rise to a non-uniform potential profile along the length of the wire.

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To account for this we implement the gate potential as a hyperbolic tangent function as described in [29]. This can result in FP oscillations in pristine wires without any defects. The blue curve in figure 5(b) shows the conductance, $G$, in units of ${G_0}$ as a function of gate voltage. The results obtained from our simulation, blue curve in figure 5(b), agree qualitatively with the data in figure 2(b). Note that while FB oscillations are expected generically, the details of the FB interference pattern are device-specific because of variation in disorder, contact transparency and the geometry of each device.

In conclusion, we fabricated ∼10 μm long and ∼55 nm wide InSb NW. We used FLG as the conducting layer for the back gate, yielding reduced surface roughness relative to Ti/Au back gates. The electrical properties of the thin InSb NW with FLG-AlO_x local back gate were measured at low temperatures. By leveraging the large length of the NW (∼10 μm) we explored electronic transport in the diffusive transport regime on the same wire on which the ballistic regime was also accessed, the first with contact spacing of ∼6 μm and the second with contact spacing of ∼200 nm. In the ballistic regime, the devices reveal Fabry–Pérot interference due to multiple partial reflections of the phase-coherently propagating electron waves. The visibility of the Fabry–Pérot oscillations competes with that of conductance plateaus, yet the plateaus remain detectable, suggesting that for the channel length of ∼200 nm transport occurs phase-coherently and ballistically through a few discrete quantum modes. Quantized conductance at zero magnetic field has been very difficult to observe in InSb NW devices [30] and remains a key test for a device's suitability for MZM experiments. Our results suggest that reducing the NW diameter, along with optimizing gate materials could be a viable path towards establishing a suitable electronic regime for MZMs.

This work was supported by the Department of Energy under Award No. DE-SC0019274. Portions of this work were conducted in the Minnesota Nano Center, which is supported by the National Science Foundation through the National Nanotechnology Coordinated Infrastructure (NNCI) under Award Number ECCS-2025124. Parts of this work were carried out in the Characterization Facility, University of Minnesota, which receives partial support from the NSF through the MRSEC (Award Number DMR-2011401) and the NNCI (Award Number ECCS-2025124) programs. This work was supported by the European Research Council (ERC TOCINA 834290). The authors recognize Solliance, a solar energy R&D initiative of ECN, TNO, Holst, TU/e, IMEC and Forschungszentrum Jülich, and the Dutch province of Noord-Brabant for funding the TEM facility. TU/e acknowledges the research program 'Materials for the Quantum Age' (QuMat) for financial support. This program (Registration Number 024.005.006) is part of the Gravitation program financed by the Dutch Ministry of Education, Culture and Science (OCW).

All data that support the findings of this study are included within the article (and any supplementary files).