std_detect/detect/arch/
riscv.rs

1//! Run-time feature detection on RISC-V.
2
3features! {
4    @TARGET: riscv;
5    @CFG: any(target_arch = "riscv32", target_arch = "riscv64");
6    @MACRO_NAME: is_riscv_feature_detected;
7    @MACRO_ATTRS:
8    /// A macro to test at *runtime* whether instruction sets are available on
9    /// RISC-V platforms.
10    ///
11    /// RISC-V standard defined the base sets and the extension sets.
12    /// The base sets are RV32I, RV64I, RV32E or RV128I. Any RISC-V platform
13    /// must support one base set and/or multiple extension sets.
14    ///
15    /// Any RISC-V standard instruction sets can be in state of either ratified,
16    /// frozen or draft. The version and status of current standard instruction
17    /// sets can be checked out from preface section of the [ISA manual].
18    ///
19    /// Platform may define and support their own custom instruction sets with
20    /// ISA prefix X. These sets are highly platform specific and should be
21    /// detected with their own platform support crates.
22    ///
23    /// [ISA manual]: https://riscv.org/specifications/ratified/
24    ///
25    /// # Platform-specific/agnostic Behavior and Availability
26    ///
27    /// Runtime detection depends on the platform-specific feature detection
28    /// facility and its availability per feature is
29    /// highly platform/version-specific.
30    ///
31    /// Still, a best-effort attempt is performed to enable subset/dependent
32    /// features if a superset feature is enabled regardless of the platform.
33    /// For instance, if the A extension (`"a"`) is enabled, its subsets (the
34    /// Zalrsc and Zaamo extensions; `"zalrsc"` and `"zaamo"`) are also enabled.
35    /// Likewise, if the F extension (`"f"`) is enabled, one of its dependencies
36    /// (the Zicsr extension `"zicsr"`) is also enabled.
37    ///
38    /// # Unprivileged Specification
39    ///
40    /// The supported ratified RISC-V instruction sets are as follows:
41    ///
42    /// * RV32E: `"rv32e"`
43    /// * RV32I: `"rv32i"`
44    /// * RV64I: `"rv64i"`
45    /// * A: `"a"`
46    ///   * Zaamo: `"zaamo"`
47    ///   * Zalrsc: `"zalrsc"`
48    /// * B: `"b"`
49    ///   * Zba: `"zba"`
50    ///   * Zbb: `"zbb"`
51    ///   * Zbs: `"zbs"`
52    /// * C: `"c"`
53    ///   * Zca: `"zca"`
54    ///   * Zcd: `"zcd"` (if D is enabled)
55    ///   * Zcf: `"zcf"` (if F is enabled on RV32)
56    /// * D: `"d"`
57    /// * F: `"f"`
58    /// * M: `"m"`
59    /// * Q: `"q"`
60    /// * V: `"v"`
61    ///   * Zve32x: `"zve32x"`
62    ///   * Zve32f: `"zve32f"`
63    ///   * Zve64x: `"zve64x"`
64    ///   * Zve64f: `"zve64f"`
65    ///   * Zve64d: `"zve64d"`
66    /// * Zicbom: `"zicbom"`
67    /// * Zicboz: `"zicboz"`
68    /// * Zicntr: `"zicntr"`
69    /// * Zicond: `"zicond"`
70    /// * Zicsr: `"zicsr"`
71    /// * Zifencei: `"zifencei"`
72    /// * Zihintntl: `"zihintntl"`
73    /// * Zihintpause: `"zihintpause"`
74    /// * Zihpm: `"zihpm"`
75    /// * Zimop: `"zimop"`
76    /// * Zabha: `"zabha"`
77    /// * Zacas: `"zacas"`
78    /// * Zawrs: `"zawrs"`
79    /// * Zfa: `"zfa"`
80    /// * Zfbfmin: `"zfbfmin"`
81    /// * Zfh: `"zfh"`
82    ///   * Zfhmin: `"zfhmin"`
83    /// * Zfinx: `"zfinx"`
84    /// * Zdinx: `"zdinx"`
85    /// * Zhinx: `"zhinx"`
86    ///   * Zhinxmin: `"zhinxmin"`
87    /// * Zcb: `"zcb"`
88    /// * Zcmop: `"zcmop"`
89    /// * Zbc: `"zbc"`
90    /// * Zbkb: `"zbkb"`
91    /// * Zbkc: `"zbkc"`
92    /// * Zbkx: `"zbkx"`
93    /// * Zk: `"zk"`
94    /// * Zkn: `"zkn"`
95    ///   * Zknd: `"zknd"`
96    ///   * Zkne: `"zkne"`
97    ///   * Zknh: `"zknh"`
98    /// * Zkr: `"zkr"`
99    /// * Zks: `"zks"`
100    ///   * Zksed: `"zksed"`
101    ///   * Zksh: `"zksh"`
102    /// * Zkt: `"zkt"`
103    /// * Zvbb: `"zvbb"`
104    /// * Zvbc: `"zvbc"`
105    /// * Zvfbfmin: `"zvfbfmin"`
106    /// * Zvfbfwma: `"zvfbfwma"`
107    /// * Zvfh: `"zvfh"`
108    ///   * Zvfhmin: `"zvfhmin"`
109    /// * Zvkb: `"zvkb"`
110    /// * Zvkg: `"zvkg"`
111    /// * Zvkn: `"zvkn"`
112    ///   * Zvkned: `"zvkned"`
113    ///   * Zvknha: `"zvknha"`
114    ///   * Zvknhb: `"zvknhb"`
115    /// * Zvknc: `"zvknc"`
116    /// * Zvkng: `"zvkng"`
117    /// * Zvks: `"zvks"`
118    ///   * Zvksed: `"zvksed"`
119    ///   * Zvksh: `"zvksh"`
120    /// * Zvksc: `"zvksc"`
121    /// * Zvksg: `"zvksg"`
122    /// * Zvkt: `"zvkt"`
123    /// * Ztso: `"ztso"`
124    ///
125    /// There's also bases and extensions marked as standard instruction set,
126    /// but they are in frozen or draft state. These instruction sets are also
127    /// reserved by this macro and can be detected in the future platforms.
128    ///
129    /// Draft RISC-V instruction sets:
130    ///
131    /// * RV128I: `"rv128i"`
132    /// * J: `"j"`
133    /// * P: `"p"`
134    /// * Zam: `"zam"`
135    ///
136    /// # Performance Hints
137    ///
138    /// The two features below define performance hints for unaligned
139    /// scalar/vector memory accesses, respectively.  If enabled, it denotes that
140    /// corresponding unaligned memory access is reasonably fast.
141    ///
142    /// * `"unaligned-scalar-mem"`
143    ///   * Runtime detection requires Linux kernel version 6.4 or later.
144    /// * `"unaligned-vector-mem"`
145    ///   * Runtime detection requires Linux kernel version 6.13 or later.
146    #[stable(feature = "riscv_ratified", since = "1.78.0")]
147
148    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32i: "rv32i";
149    without cfg check: true;
150    /// RV32I Base Integer Instruction Set
151    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32e: "rv32e";
152    without cfg check: true;
153    /// RV32E Base Integer Instruction Set
154    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv64i: "rv64i";
155    without cfg check: true;
156    /// RV64I Base Integer Instruction Set
157    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv128i: "rv128i";
158    without cfg check: true;
159    /// RV128I Base Integer Instruction Set
160
161    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] unaligned_scalar_mem: "unaligned-scalar-mem";
162    /// Has reasonably performant unaligned scalar
163    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] unaligned_vector_mem: "unaligned-vector-mem";
164    /// Has reasonably performant unaligned vector
165
166    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicsr: "zicsr";
167    /// "Zicsr" Extension for Control and Status Register (CSR) Instructions
168    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicntr: "zicntr";
169    /// "Zicntr" Extension for Base Counters and Timers
170    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihpm: "zihpm";
171    /// "Zihpm" Extension for Hardware Performance Counters
172    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zifencei: "zifencei";
173    /// "Zifencei" Extension for Instruction-Fetch Fence
174
175    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintntl: "zihintntl";
176    /// "Zihintntl" Extension for Non-Temporal Locality Hints
177    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintpause: "zihintpause";
178    /// "Zihintpause" Extension for Pause Hint
179    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zimop: "zimop";
180    /// "Zimop" Extension for May-Be-Operations
181    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicbom: "zicbom";
182    /// "Zicbom" Extension for Cache-Block Management Instructions
183    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicboz: "zicboz";
184    /// "Zicboz" Extension for Cache-Block Zero Instruction
185    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicond: "zicond";
186    /// "Zicond" Extension for Integer Conditional Operations
187
188    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] m: "m";
189    /// "M" Extension for Integer Multiplication and Division
190
191    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] a: "a";
192    /// "A" Extension for Atomic Instructions
193    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zalrsc: "zalrsc";
194    /// "Zalrsc" Extension for Load-Reserved/Store-Conditional Instructions
195    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zaamo: "zaamo";
196    /// "Zaamo" Extension for Atomic Memory Operations
197    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zawrs: "zawrs";
198    /// "Zawrs" Extension for Wait-on-Reservation-Set Instructions
199    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zabha: "zabha";
200    /// "Zabha" Extension for Byte and Halfword Atomic Memory Operations
201    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zacas: "zacas";
202    /// "Zacas" Extension for Atomic Compare-and-Swap (CAS) Instructions
203    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam";
204    without cfg check: true;
205    /// "Zam" Extension for Misaligned Atomics
206    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] ztso: "ztso";
207    /// "Ztso" Extension for Total Store Ordering
208
209    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] f: "f";
210    /// "F" Extension for Single-Precision Floating-Point
211    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] d: "d";
212    /// "D" Extension for Double-Precision Floating-Point
213    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] q: "q";
214    without cfg check: true;
215    /// "Q" Extension for Quad-Precision Floating-Point
216    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfh: "zfh";
217    /// "Zfh" Extension for Half-Precision Floating-Point
218    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfhmin: "zfhmin";
219    /// "Zfhmin" Extension for Minimal Half-Precision Floating-Point
220    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfa: "zfa";
221    /// "Zfa" Extension for Additional Floating-Point Instructions
222    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfbfmin: "zfbfmin";
223    /// "Zfbfmin" Extension for Scalar BF16 Converts
224
225    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfinx: "zfinx";
226    /// "Zfinx" Extension for Single-Precision Floating-Point in Integer Registers
227    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zdinx: "zdinx";
228    /// "Zdinx" Extension for Double-Precision Floating-Point in Integer Registers
229    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zhinx: "zhinx";
230    /// "Zhinx" Extension for Half-Precision Floating-Point in Integer Registers
231    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zhinxmin: "zhinxmin";
232    /// "Zhinxmin" Extension for Minimal Half-Precision Floating-Point in Integer Registers
233
234    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] c: "c";
235    /// "C" Extension for Compressed Instructions
236    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zca: "zca";
237    /// "Zca" Compressed Instructions excluding Floating-Point Loads/Stores
238    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcf: "zcf";
239    without cfg check: true;
240    /// "Zcf" Compressed Instructions for Single-Precision Floating-Point Loads/Stores on RV32
241    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcd: "zcd";
242    without cfg check: true;
243    /// "Zcd" Compressed Instructions for Double-Precision Floating-Point Loads/Stores
244    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcb: "zcb";
245    /// "Zcb" Simple Code-size Saving Compressed Instructions
246    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zcmop: "zcmop";
247    /// "Zcmop" Extension for Compressed May-Be-Operations
248
249    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] b: "b";
250    /// "B" Extension for Bit Manipulation
251    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zba: "zba";
252    /// "Zba" Extension for Address Generation
253    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbb: "zbb";
254    /// "Zbb" Extension for Basic Bit-Manipulation
255    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbc: "zbc";
256    /// "Zbc" Extension for Carry-less Multiplication
257    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbs: "zbs";
258    /// "Zbs" Extension for Single-Bit Instructions
259
260    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbkb: "zbkb";
261    /// "Zbkb" Extension for Bit-Manipulation for Cryptography
262    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbkc: "zbkc";
263    /// "Zbkc" Extension for Carry-less Multiplication for Cryptography
264    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbkx: "zbkx";
265    /// "Zbkx" Extension for Crossbar Permutations
266    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zknd: "zknd";
267    /// "Zknd" Cryptography Extension for NIST Suite: AES Decryption
268    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkne: "zkne";
269    /// "Zkne" Cryptography Extension for NIST Suite: AES Encryption
270    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zknh: "zknh";
271    /// "Zknh" Cryptography Extension for NIST Suite: Hash Function Instructions
272    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zksed: "zksed";
273    /// "Zksed" Cryptography Extension for ShangMi Suite: SM4 Block Cipher Instructions
274    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zksh: "zksh";
275    /// "Zksh" Cryptography Extension for ShangMi Suite: SM3 Hash Function Instructions
276    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkr: "zkr";
277    /// "Zkr" Entropy Source Extension
278    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkn: "zkn";
279    /// "Zkn" Cryptography Extension for NIST Algorithm Suite
280    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zks: "zks";
281    /// "Zks" Cryptography Extension for ShangMi Algorithm Suite
282    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zk: "zk";
283    /// "Zk" Cryptography Extension for Standard Scalar Cryptography
284    @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkt: "zkt";
285    /// "Zkt" Cryptography Extension for Data Independent Execution Latency
286
287    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] v: "v";
288    /// "V" Extension for Vector Operations
289    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve32x: "zve32x";
290    /// "Zve32x" Vector Extension for Embedded Processors (32-bit+; Integer)
291    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve32f: "zve32f";
292    /// "Zve32f" Vector Extension for Embedded Processors (32-bit+; with Single-Precision Floating-Point)
293    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64x: "zve64x";
294    /// "Zve64x" Vector Extension for Embedded Processors (64-bit+; Integer)
295    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64f: "zve64f";
296    /// "Zve64f" Vector Extension for Embedded Processors (64-bit+; with Single-Precision Floating-Point)
297    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zve64d: "zve64d";
298    /// "Zve64d" Vector Extension for Embedded Processors (64-bit+; with Double-Precision Floating-Point)
299    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvfh: "zvfh";
300    /// "Zvfh" Vector Extension for Half-Precision Floating-Point
301    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvfhmin: "zvfhmin";
302    /// "Zvfhmin" Vector Extension for Minimal Half-Precision Floating-Point
303    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvfbfmin: "zvfbfmin";
304    /// "Zvfbfmin" Vector Extension for BF16 Converts
305    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvfbfwma: "zvfbfwma";
306    /// "Zvfbfwma" Vector Extension for BF16 Widening Multiply-Add
307
308    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvbb: "zvbb";
309    /// "Zvbb" Extension for Vector Basic Bit-Manipulation
310    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvbc: "zvbc";
311    /// "Zvbc" Extension for Vector Carryless Multiplication
312    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkb: "zvkb";
313    /// "Zvkb" Extension for Vector Cryptography Bit-Manipulation
314    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkg: "zvkg";
315    /// "Zvkg" Cryptography Extension for Vector GCM/GMAC
316    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkned: "zvkned";
317    /// "Zvkned" Cryptography Extension for NIST Suite: Vector AES Block Cipher
318    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknha: "zvknha";
319    /// "Zvknha" Cryptography Extension for Vector SHA-2 Secure Hash (SHA-256)
320    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknhb: "zvknhb";
321    /// "Zvknhb" Cryptography Extension for Vector SHA-2 Secure Hash (SHA-256/512)
322    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksed: "zvksed";
323    /// "Zvksed" Cryptography Extension for ShangMi Suite: Vector SM4 Block Cipher
324    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksh: "zvksh";
325    /// "Zvksh" Cryptography Extension for ShangMi Suite: Vector SM3 Secure Hash
326    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkn: "zvkn";
327    /// "Zvkn" Cryptography Extension for NIST Algorithm Suite
328    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvknc: "zvknc";
329    /// "Zvknc" Cryptography Extension for NIST Algorithm Suite with Carryless Multiply
330    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkng: "zvkng";
331    /// "Zvkng" Cryptography Extension for NIST Algorithm Suite with GCM
332    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvks: "zvks";
333    /// "Zvks" Cryptography Extension for ShangMi Algorithm Suite
334    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksc: "zvksc";
335    /// "Zvksc" Cryptography Extension for ShangMi Algorithm Suite with Carryless Multiply
336    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvksg: "zvksg";
337    /// "Zvksg" Cryptography Extension for ShangMi Algorithm Suite with GCM
338    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zvkt: "zvkt";
339    /// "Zvkt" Extension for Vector Data-Independent Execution Latency
340
341    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] j: "j";
342    without cfg check: true;
343    /// "J" Extension for Dynamically Translated Languages
344    @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] p: "p";
345    without cfg check: true;
346    /// "P" Extension for Packed-SIMD Instructions
347}
std_detect/detect/arch/riscv.rs

std_detect/detect/arch/
riscv.rs
