Generating unusual instruction

Project Infrastructure LLVM Dev List Archives
1

I have seen that most of the targets do comparison and branching
in two separate instructions e.g. 'cmpl' followed by 'br' in x86 or the
like.
LLVM IR is also in same manner.

I want to implement comparison+branching in one instruction like

       beq r1, r2, .label #if r1==r2 then jump to .label

How to merge two instruction into one.

Regards
Vikram Singh

2

Hi,

Have you try to directly describe such patterns in tblgen file? Like this:
(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)

MIPS backend does that. I also do this in my own backend, and seem to be working fine.

3

Thanks, I tried to go thru the Mips code to see the code related to the
branch implementation. But there are many fragments in the MipsInstrInfo.td
and also many Pat statements. Please help me in regard of these points.
1. I find it, as it seems to me, hard to refer Mips because I already have
taken Sparc code. Is there any way to modify Sparc code for eliminate SUBCC.
2. I find less literature on the .td file. for example consider
     [brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset, IIBranch]
    What is IIBranch.
3. What are these ZextLoad and the likes?

Regards
Vikram

4

Hi Dongrui

I looked for MIPS tblgen .td file but in case MIPS also it is (1) first
subtracting the two operand and then (2) comparing the result with
zero. i.e. it is generating two insns. But i want that in just one.

Any help.....

Regard
VSP