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ORCIDNoureddine Chabini
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2020 – today
- 2024
[c27]Noureddine Chabini, Marilyn Claire Wolf, Rachid Beguenane:
LUT-Based Multipliers for IEEE-754 Floating Point Arithmetic on FPGAs. UEMCON 2024: 698-701- 2023
- [j16]Samir Dahmani
, Mountassar Maamoun, Ghania Zerari, Noureddine Chabini, Rachid Beguenane:
An Efficient FPGA-Based Gaussian Random Number Generator Using an Accurate Segmented Box-Muller Method. IEEE Access 11: 64745-64757 (2023) - [c26]Noureddine Chabini, Marilyn Claire Wolf:
Path Balancing for Reducing Dynamic Power Consumption in Digital Designs Containing IP-Blocks. AIIoT 2023: 730-735 - [c25]Noureddine Chabini, Rachid Beguenane:
FPGA-Based 8x8 Bits Signed Multipliers Using LUTs. CCECE 2023: 366-370 - [c24]Justin Woelfle, Noureddine Chabini, Rachid Beguenane:
Comparing FPGA-Based Adders and Application to the Implementation of a Digital FIR Filter. CCECE 2023: 377-380 - [c23]Noureddine Chabini, Rachid Beguenane:
FPGA-Based Digital FIR Filters With Small Coefficients and Large Data Input. CCWC 2023: 218-221 - 2022
- [j15]Mohamed Najoui, Mounir Bahtat, Abdessamad Klilou, Anas Hatim, Said Belkouch, Atman Jbari, Noureddine Chabini:
Ultra-fast and efficient implementation schemes of complex matrix multiplication algorithm for VLIW architectures. Comput. Electr. Eng. 102: 108294 (2022) - [c22]Noureddine Chabini, Rachid Beguenane:
FPGA-Based Designs of the Factorial Function. CCECE 2022: 16-20 - [c21]Noureddine Chabini, Said Belkouch, Mohamed Najoui:
An Algorithm for Gate Resizing to Reduce Power Dissipation in Combinational Digital Designs. ICECOCS 2022: 1-3 - 2021
- [j14]Mountassar Maamoun, Adnane Hassani, Samir Dahmani, Hocine Ait Saadi, Ghania Zerari, Noureddine Chabini, Rachid Beguenane:
Efficient FPGA based architecture for high-order FIR filtering using simultaneous DSP and LUT reduced utilization. IET Circuits Devices Syst. 15(5): 475-484 (2021) - 2020
- [j13]Mohamed Najoui, Anas Hatim, Said Belkouch, Noureddine Chabini:
Novel Implementation Approach with Enhanced Memory Access Performance of MGS Algorithm for VLIW Architecture. J. Circuits Syst. Comput. 29(12): 2050200:1-2050200:23 (2020)
2010 – 2019
- 2017
- [j12]Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini:
Efficient Realization of BCD Multipliers Using FPGAs. Int. J. Reconfigurable Comput. 2017: 2410408:1-2410408:12 (2017) - [j11]Mohamed Najoui, Mounir Bahtat, Anas Hatim, Said Belkouch, Noureddine Chabini:
VLIW DSP-Based Low-Level Instruction Scheme of Givens QR Decomposition for Real-Time Processing. J. Circuits Syst. Comput. 26(9): 1750129:1-1750129:26 (2017) - [c20]Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini:
Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier. CCECE 2017: 1-6 - 2015
- [c19]Noureddine Chabini, Said Belkouch:
Area and delay aware approaches for realizing multi-operand addition on FPGAs using two-operand adders. AICCSA 2015: 1-4 - [c18]Fatima-Ezzahra Guessous, Noureddine Chabini:
Reducing the number of embedded multipliers in squaring large size complex numbers. ICM 2015: 25-26 - 2013
- [j10]Anas Hatim, Said Belkouch, Mohamed El Aakif, Moha M'rabet Hassani, Noureddine Chabini:
Design optimization of the quantization and a pipelined 2D-DCT for real-time applications. Multim. Tools Appl. 67(3): 667-685 (2013) - 2012
- [j9]Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois:
Asymmetric large size multipliers with optimised FPGA resource utilisation. IET Comput. Digit. Tech. 6(6): 372-383 (2012) - [c17]Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini:
An improved BCD adder using 6-LUT FPGAs. NEWCAS 2012: 13-16 - 2011
- [j8]Noureddine Chabini, Marilyn Wolf:
Reordering the assembly instructions in basic blocks to reduce switching activities on the instruction bus. IET Comput. Digit. Tech. 5(5): 386-392 (2011) - [c16]Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini:
Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs. ICECS 2011: 137-140 - [c15]Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini:
Asymmetric Large Size Signed Multipliers Using Embedded Blocks in FPGAs. IPDPS Workshops 2011: 271-277 - 2010
- [j7]Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois:
FPGA-Based Efficient Design Approaches for Large Size Two's Complement Squarers. J. Signal Process. Syst. 58(1): 3-15 (2010)
2000 – 2009
- 2009
- [j6]Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini:
Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs. Int. J. Reconfigurable Comput. 2009: 145130:1-145130:11 (2009) - [c14]Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini:
Two level decomposition based matrix multiplication for FPGAs. ICECS 2009: 427-430 - 2007
- [j5]Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois:
Optimised realisations of large integer multipliers and squarers using embedded blocks. IET Comput. Digit. Tech. 1(1): 9-16 (2007) - [c13]Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois:
FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers. ASAP 2007: 18-23 - [c12]Noureddine Chabini, Wayne H. Wolf:
An approach for computing the initial state for retimed synchronous sequential circuits. HLDVT 2007: 123-130 - [c11]Noureddine Chabini, Wayne H. Wolf:
Register binding guided by the size of variables. ICCD 2007: 587-594 - [c10]Noureddine Chabini, Wayne H. Wolf:
Reducing the Code Size of Retimed Software Loops under Timing and Resource Constraints. IESS 2007: 255-268 - [c9]Noureddine Chabini:
A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs. PATMOS 2007: 64-74 - 2006
- [c8]Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois:
An Optimized Design Approach for Squaring Large Integers Using Embedded Hardwired Multipliers. AICCSA 2006: 248-254 - [c7]Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois:
Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded Multipliers. SoCC 2006: 21-24 - 2005
- [j4]Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria:
Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques. ACM Trans. Design Autom. Electr. Syst. 10(2): 187-204 (2005) - [j3]Noureddine Chabini, Wayne H. Wolf:
Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints. IEEE Trans. Very Large Scale Integr. Syst. 13(10): 1113-1126 (2005) - 2004
- [j2]Noureddine Chabini, Wayne H. Wolf:
Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling. IEEE Trans. Very Large Scale Integr. Syst. 12(6): 573-589 (2004) - [c6]Noureddine Chabini, Wayne H. Wolf:
An approach for reducing dynamic power consumption in synchronous sequential digital designs. ASP-DAC 2004: 198-204 - [c5]Noureddine Chabini, Wayne H. Wolf:
An approach for integrating basic retiming and software pipelining. EMSOFT 2004: 287-296 - 2003
- [j1]Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria:
Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 346-351 (2003) - [c4]Noureddine Chabini, Wayne H. Wolf:
Minimizing Variables' Lifetime in Loop-Intensive Applications. EMSOFT 2003: 100-116 - [c3]Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria:
Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs. ACM Great Lakes Symposium on VLSI 2003: 221-224 - 2001
- [c2]Noureddine Chabini, El Mostapha Aboulhamid, Yvon Savaria:
Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages. ICCD 2001: 546-552 - [c1]Noureddine Chabini, Yvon Savaria:
Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques. ISSS 2001: 209-214
Coauthor Index
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