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Ranga Vemuri
2020 – today
- 2024
- [c245]Haimanti Chakraborty, Ranga Vemuri:
RTL Interconnect Obfuscation By Polymorphic Switch Boxes For Secure Hardware Generation. ISQED 2024: 1-8 - [c244]Padmaja Bhamidipati, Ranga Vemuri:
QA-NoCs: Quantitative Analysis for Trojan Detection in Network-on-Chips. ISVLSI 2024: 757-761 - [c243]Juneet Kumar Meka, Ranga Vemuri:
ACT: Attributed Circuit Transformation System for Synthetic Circuit Generation. MWSCAS 2024: 350-356 - [c242]Padmaja Bhamidipati, Ranga Vemuri:
NoC-Armor: Leveraging Quantitative Analysis for Enhanced Security. MWSCAS 2024: 1001-1006 - [c241]Haimanti Chakraborty, Ranga Vemuri:
Combined Split Manufacturing and Logic Obfuscation Based on Emerging Technologies at High Level for Secure 3D IC Design. MWSCAS 2024: 1403-1407 - [c240]Juneet Kumar Meka, Satya AmarKant Marupureddy, Ranga Vemuri:
Pattern Based Synthetic Benchmark Generation for Hardware Security Applications. VLSID 2024: 461-466 - [c239]Haimanti Chakraborty, Ranga Vemuri:
ROBUST: RTL OBfuscation USing Bi-functional Polymorphic OperaTors. VLSID 2024: 499-504 - [c238]Nikhil Saxena, Ranga Vemuri:
Enhancing Output Corruption Through GSHE Switch Based Logic Encryption. VLSID 2024: 505-510 - [c237]Suriya Srinivasan, Ranga Vemuri:
Trojan Localization Using Information Flow Tracking Properties in SoC Designs. VLSID 2024: 523-528 - [i6]Haimanti Chakraborty, Ranga Vemuri:
RTL Interconnect Obfuscation By Polymorphic Switch Boxes For Secure Hardware Generation. CoRR abs/2404.07426 (2024) - 2023
- [j30]Nikhil Saxena
, Ranga Vemuri
:
Hybrid Shielding: Amplifying the Power of Camouflaging and Logic Encryption. IEEE Access 11: 128484-128499 (2023) - [c236]Juneet Kumar Meka, Ranga Vemuri:
Attributed Graph Transformation for Generating Synthetic Benchmarks for Hardware Security. ISQED 2023: 1-9 - [c235]Ram Venkat Narayanan, Aparajithan Nathamuni Venkatesan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri:
Reverse Engineering Word-Level Models from Look-Up Table Netlists. ISQED 2023: 1-8 - [c234]Sundarakumar Muthukumaran, Aparajithan Nathamuni Venkatesan, Kishore Pula, Ram Venkat Narayanan, Ranga Vemuri, John Marty Emmert:
Reverse Engineering of RTL Controllers from Look-Up Table Netlists. ISVLSI 2023: 1-6 - [c233]Kishore Pula, Aparajithan Nathamuni Venkatesan, Ram Venkat Narayanan, Sundarakumar Muthukumaran, Ranga Vemuri, John Marty Emmert:
RELUT-GNN: Reverse Engineering Data Path Elements From LUT Netlists Using Graph Neural Networks. MWSCAS 2023: 511-515 - [c232]Haimanti Chakraborty, Ranga Vemuri:
Split Manufacturing Based Secure Hardware Design by BEOL Signal Selection In High Level Synthesis. MWSCAS 2023: 1083-1087 - [c231]Nikhil Saxena, Ranga Vemuri:
Hybrid Shielding: Amplifying the Power of Camouflaging and Logic Encryption. MWSCAS 2023: 1103-1107 - [c230]Padmaja Bhamidipati, Ranga Vemuri:
ASPIRE: An Intermediate Representation for Abstract Security Policies. VLSID 2023: 175-180 - [c229]Suriya Srinivasan, Ranga Vemuri:
Mutation Analysis and Model Checking Guided Test Generation for SoC Run-Time Monitors. VLSID 2023: 240-245 - [c228]Aparajithan Nathamuni Venkatesan, Ram Venkat Narayanan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri:
Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information. VLSID 2023: 389-394 - [i5]Ram Venkat Narayanan, Aparajithan Nathamuni Venkatesan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri:
Reverse Engineering Word-Level Models from Look-Up Table Netlists. CoRR abs/2303.02762 (2023) - [i4]Aparajithan Nathamuni Venkatesan, Ram Venkat Narayanan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri:
Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information. CoRR abs/2303.07405 (2023) - 2022
- [c227]Khitam M. Alatoun, Ranga Vemuri:
Efficient Method for Timing-based Information Flow Verification in Hardware Designs. ACM Great Lakes Symposium on VLSI 2022: 159-163 - [c226]Suriya Srinivasan, Ranga Vemuri:
Model Checking Leveraged Error Localization for Complex RTL Designs. ICCD 2022: 585-592 - [c225]Juneet Kumar Meka, Shrinidhi Venkatesh, Ranga Vemuri:
Analysis of the Satisfiability Attack Against Logic Encryption Using Synthetic Benchmarks. iSES 2022: 445-450 - [c224]Nikhil Saxena
, Ranga Vemuri:
ISPLock: A Hybrid Internal State Locking Method Using Polymorphic Gates. ISVLSI 2022: 140-145 - [c223]Christopher Chuvalas, Ranga Vemuri:
FPGA Acceleration of a Stochastic Local Search Portfolio Solver for Boolean Satisfiability. MWSCAS 2022: 1-4 - [c222]Christopher Chuvalas, Ranga Vemuri:
FPGA-Based Stochastic Local Search Satisfiability Solvers Exploiting High Bandwidth Memory. VLSI-SoC 2022: 1-6 - [p2]Richa Agrawal, Ranga Vemuri:
Encoding of Finite-State Controllers for Graded Security and Power. Behavioral Synthesis for Hardware Security 2022: 147-175 - [p1]Mike Borowczak
, Ranga Vemuri:
S*FSMs for Reduced Information Leakage: Power Side Channel Protection Through Secure Encoding. Behavioral Synthesis for Hardware Security 2022: 319-342 - 2021
- [j29]David M. Luria
, Ranga Vemuri
:
Logic Encryption for Resource Constrained Designs. IEEE Access 9: 29312-29345 (2021) - [c221]Khitam M. Alatoun, Shanmukha Murali Achyutha, Ranga Vemuri:
Efficient Methods for SoC Trust Validation Using Information Flow Verification. ICCD 2021: 608-616 - [c220]Nikhil Saxena
, Ram Venkat Narayanan, Juneet Kumar Meka, Ranga Vemuri:
SRTLock: A Sensitivity Resilient Two-Tier Logic Encryption Scheme. iSES 2021: 389-394 - [c219]Khitam Alatoun, Bharath Shankaranarayanan, Shanmukha Murali Achyutha, Ranga Vemuri
:
SoC Trust Validation Using Assertion-Based Security Monitors. ISQED 2021: 496-503 - [c218]Subashree Raja, Padmaja Bhamidipati, Xiaobang Liu, Ranga Vemuri
:
Security Capsules: An Architecture for Post-Silicon Security Assertion Validation for Systems-on-Chip. ISVLSI 2021: 248-253 - [c217]Padmaja Bhamidipati, Shanmukha Murali Achyutha, Ranga Vemuri:
Security Analysis of a System-on-Chip Using Assertion-Based Verification. MWSCAS 2021: 826-831 - [c216]Carla Purdy, John Marty Emmert, Rashmi Jha, Ranga Vemuri
:
Educating the Next Generation of Cybersecurity Defenders at the University of Cincinnati. MWSCAS 2021: 836-839 - 2020
- [c215]Suprajaa Tummala, Xiaobang Liu, Ranga Vemuri
:
Signal Selection Heuristics for Post-Silicon Validation. ISQED 2020: 401-407 - [c214]Yasaswy Kasarabada, Vaishali Muralidharan, Ranga Vemuri
:
SLED: Sequential Logic Encryption Using Dynamic Keys. MWSCAS 2020: 844-847 - [c213]Yasaswy Kasarabada, Ranga Vemuri
:
StateLock: State Transition Based Logic Locking for Sequential Circuits. VLSID 2020: 171-176
2010 – 2019
- 2019
- [j28]Richa Agrawal, Ranga Vemuri
, Mike Borowczak
:
A State Machine Encoding Methodology Against Power Analysis Attacks. J. Electron. Test. 35(5): 621-639 (2019) - [j27]Mike Borowczak
, Ranga Vemuri
:
Mitigating information leakage during critical communication using S*FSM. IET Comput. Digit. Tech. 13(4): 292-301 (2019) - [c212]Suyuan Chen, Ranga Vemuri
:
Exploiting Proximity Information in a Satisfiability Based Attack Against Split Manufactured Circuits. HOST 2019: 171-180 - [c211]Yasaswy Kasarabada, David M. Luria, Ranga Vemuri
:
Trust in IoT Devices: A Logic Encryption Perspective. IFIPIoT 2019: 123-141 - [c210]Yasaswy Kasarabada
, Suyuan Chen, Ranga Vemuri
:
On SAT-Based Attacks On Encrypted Sequential Logic Circuits. ISQED 2019: 204-211 - [c209]Xiaobang Liu, Ranga Vemuri
:
Assertion Coverage Aware Trace Signal Selection in Post-Silicon Validation. ISQED 2019: 271-277 - [c208]Yasaswy Kasarabada, Sudheer Ram Thulasi Raman, Ranga Vemuri
:
Deep State Encryption for Sequential Logic Circuits. ISVLSI 2019: 338-343 - [c207]Harsh Vamja, Richa Agrawal, Ranga Vemuri
:
Non-Invasive Reverse Engineering of Finite State Machines Using Power Analysis and Boolean Satisfiability. MWSCAS 2019: 452-455 - [c206]Richa Agrawal, Mike Borowczak
, Ranga Vemuri
:
A State Encoding Methodology for Side-Channel Security vs. Power Trade-off Exploration. VLSID 2019: 70-75 - [i3]Harsh Vamja, Richa Agrawal, Ranga Vemuri:
Non-Invasive Reverse Engineering of Finite State Machines Using Power Analysis and Boolean Satisfiability. CoRR abs/1908.01979 (2019) - 2018
- [c205]Suyuan Chen, Ranga Vemuri
:
Improving the Security of Split Manufacturing Using a Novel BEOL Signal Selection Method. ACM Great Lakes Symposium on VLSI 2018: 135-140 - [c204]Richa Agrawal, Ranga Vemuri
:
On state encoding against power analysis attacks for finite state controllers. HOST 2018: 181-186 - [c203]Suyuan Chen, Ranga Vemuri
:
Reverse Engineering of Split Manufactured Sequential Circuits Using Satisfiability Checking. ICCD 2018: 530-536 - [c202]Renuka Lokare, Ranga Vemuri
:
Progressive and secure performance unlocking for digital integrated circuits. ICCE 2018: 1-6 - [c201]Ankita Manjunath Nayak, Ranga Vemuri
:
A secure tunable-precision architecture for image processing applications. ICCE 2018: 1-5 - [c200]Xiaobang Liu, Ranga Vemuri
:
Fast Heuristics for Near-Optimal Signal Restoration in Post-Silicon Validation. ISVLSI 2018: 34-39 - [c199]Pranav Dharmadhikari, Akhilesh Raju, Ranga Vemuri
:
Detection of Sequential Trojans in Embedded System Designs Without Scan Chains. ISVLSI 2018: 678-683 - [c198]Suyuan Chen, Ranga Vemuri
:
On the Effectiveness of the Satisfiability Attack on Split Manufactured Circuits. VLSI-SoC 2018: 83-88 - [c197]Xiaobang Liu, Ranga Vemuri
:
Combined Inference and Satisfiability Based Methods for Complete Signal Restoration in Post-Silicon Validation. VLSID 2018: 416-421 - 2017
- [c196]Xiaobang Liu, Ranga Vemuri
:
Effective Signal Restoration in Post-Silicon Validation. ICCD 2017: 169-176 - 2016
- [j26]Haibo Yi, Shaohua Tang, Ranga Vemuri
:
Fast Inversions in Small Finite Fields by Using Binary Trees. Comput. J. 59(7): 1102-1112 (2016) - [c195]Prabanjan Komari, Ranga Vemuri
:
A novel simulation based approach for trace signal selection in silicon debug. ICCD 2016: 193-200 - 2014
- [c194]Mike Borowczak
, Ranga Vemuri
:
Enabling Side Channel Secure FSMs in the Presence of Low Power Requirements. ISVLSI 2014: 232-235 - [c193]Ramesh Nair, Ranga Vemuri
:
MITH-Dyn: A multi Vth dynamic logic design style using mixed mode FinFETs. SoCC 2014: 140-145 - 2013
- [c192]Mike Borowczak
, Ranga Vemuri
:
Secure controllers: Requirements of S*FSM. MWSCAS 2013: 553-557 - [c191]Venkat Krishnan Balasubramanian, Hao Xu, Ranga Vemuri
:
Design automation flow for voltage adaptive optimum granularity LITHE for sequential circuits. SoCC 2013: 355-360 - 2012
- [c190]Annie Avakian, Natwar Agrawal, Ranga Vemuri
:
Reconfigurable Multicore Architecture for Dynamic Processor Reallocation. ARC 2012: 329-334 - [c189]Lakshmi Narasimhan Ramakrishnan, Manoj Chakkaravarthy, Antarpreet Singh Manchanda, Mike Borowczak
, Ranga Vemuri
:
SDMLp: On the use of complementary Pass transistor Logic for design of DPA resistant circuits. HOST 2012: 31-36 - [c188]Aishwariya Pattabiraman, Annie Avakian, Ranga Vemuri
:
A Heterogeneous Cache Distribution with Reconfigurable Interconnect. IPDPS Workshops 2012: 271-276 - 2011
- [j25]Hao Xu, Ranga Vemuri
, Wen-Ben Jone:
Dynamic Characteristics of Power Gating During Mode Transition. IEEE Trans. Very Large Scale Integr. Syst. 19(2): 237-249 (2011) - [j24]Hao Xu, Wen-Ben Jone, Ranga Vemuri
:
Aggressive Runtime Leakage Control Through Adaptive Light-Weight Vth Hopping With Temperature and Process Variation. IEEE Trans. Very Large Scale Integr. Syst. 19(7): 1319-1323 (2011) - [c187]Amayika Panda, Annie Avakian, Ranga Vemuri
:
Configurable workload generators for multicore architectures. SoCC 2011: 179-184 - 2010
- [j23]Hao Xu, Wen-Ben Jone, Ranga Vemuri
:
Tuning Vth Hopping for Aggressive Runtime Leakage Control. J. Low Power Electron. 6(3): 447-456 (2010) - [c186]Hao Xu, Wen-Ben Jone, Ranga Vemuri
:
Stretching the limit of microarchitectural level leakage control with Adaptive Light-Weight Vth Hopping. ICCAD 2010: 632-636 - [c185]Hao Xu, Ranga Vemuri
, Wen-Ben Jone:
Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs. ICCAD 2010: 637-641 - [c184]Annie Avakian, Jon Nafziger, Amayika Panda, Ranga Vemuri
:
A reconfigurable architecture for multicore systems. IPDPS Workshops 2010: 1-8 - [c183]Jon Nafziger, Annie Avakian, Ranga Vemuri
:
A prediction-based, data Migration Algorithm for hybrid Architecture NoC systems. SoCC 2010: 435-440 - [c182]Hao Xu, Wen-Ben Jone, Ranga Vemuri
:
Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control. VLSI Design 2010: 51-56
2000 – 2009
- 2009
- [c181]Hao Xu, Ranga Vemuri, Wen-Ben Jone:
Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage. DATE 2009: 594-597 - [c180]Angan Das, Ranga Vemuri
:
A graph grammar based approach to automated multi-objective analog circuit design. DATE 2009: 700-705 - [c179]Balasubramanian Sethuraman, Ranga Vemuri
:
A methodology for application-specific NoC architecture generation in a dynamic task structure environment. ACM Great Lakes Symposium on VLSI 2009: 149-152 - [c178]Hao Xu, Ranga Vemuri
, Wen-Ben Jone:
Temporal and spatial idleness exploitation for optimal-grained leakage control. ICCAD 2009: 468-473 - [c177]Romana Fernandes, Ranga Vemuri
:
Accurate estimation of vector dependent leakage power in the presence of process variations. ICCD 2009: 451-458 - [c176]Almitra Pradhan, Ranga Vemuri
:
Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits. VLSI Design 2009: 131-136 - [c175]Shubhankar Basu, Balaji Kommineni, Ranga Vemuri
:
Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space. VLSI Design 2009: 433-438 - [c174]Angan Das, Ranga Vemuri
:
Fuzzy Logic Based Guidance to Graph Grammar Framework for Automated Analog Circuit Design. VLSI Design 2009: 445-450 - 2008
- [c173]Angan Das, Ranga Vemuri:
Topology synthesis of analog circuits based on adaptively generated building blocks. DAC 2008: 44-49 - [c172]Almitra Pradhan, Ranga Vemuri
:
Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches. DATE 2008: 523-526 - [c171]Angan Das, Ranga Vemuri
:
A Self-learning Optimization Technique for Topology Design of Computer Networks. EvoWorkshops 2008: 38-51 - [c170]Almitra Pradhan, Ranga Vemuri
:
A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection. ACM Great Lakes Symposium on VLSI 2008: 159-162 - [c169]Hao Xu, Wen-Ben Jone, Ranga Vemuri
:
Accurate energy breakeven time estimation for run-time power gating. ICCAD 2008: 161-168 - [c168]Hao Xu, Ranga Vemuri
, Wen-Ben Jone:
Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW. ICCD 2008: 618-625 - [c167]Angan Das, Ranga Vemuri
:
ATLAS: An adaptively formed hierarchical cell library based analog synthesis framework. ISCAS 2008: 2542-2545 - [c166]Hao Xu, Ranga Vemuri
, Wen-Ben Jone:
Dynamic virtual ground voltage estimation for power gating. ISLPED 2008: 27-32 - [c165]Shubhankar Basu, Balaji Kommineni, Ranga Vemuri
:
Variation Aware Spline Center and Range Modeling for Analog Circuit Performance. ISQED 2008: 162-167 - [c164]Shubhankar Basu, Balaji Kommineni, Ranga Vemuri
:
Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples. VLSI Design 2008: 287-293 - [c163]Almitra Pradhan, Ranga Vemuri
:
On the Use of Hash Tables for Efficient Analog Circuit Synthesis. VLSI Design 2008: 647-652 - [c162]Srividhya Rammohan, Vijay Sundaresan, Ranga Vemuri
:
Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-Resistant Secure IC Design. VLSI Design 2008: 699-705 - 2007
- [c161]Balasubramanian Sethuraman, Ranga Vemuri
:
Power variations of multi-port routers in an application-specific NoC design : A case study. ICCD 2007: 595-600 - [c160]Balaji Kommineni, Shubhankar Basu, Ranga Vemuri:
A spline based regression technique on interval valued noisy data. ICMLA 2007: 241-247 - [c159]Angan Das, Ranga Vemuri
:
GAPSYS: A GA-based Tool for Automated Passive Analog Circuit Synthesis. ISCAS 2007: 2702-2705 - [c158]Balasubramanian Sethuraman, Ranga Vemuri
:
Multicasting based topology generation and core mapping for a power efficient networks-on-chip. ISLPED 2007: 399-402 - [c157]Shubhankar Basu, Priyanka Thakore, Ranga Vemuri
:
Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques. ISQED 2007: 814-820 - [c156]Angan Das, Ranga Vemuri
:
An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms. ISVLSI 2007: 145-152 - [c155]Shubhankar Basu, Ranga Vemuri
:
Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs. ISVLSI 2007: 291-298 - [c154]Almitra Pradhan, Ranga Vemuri
:
Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit Synthesis. VLSI-SoC (Selected Papers) 2007: 1-20 - [c153]Vijay Sundaresan, Srividhya Rammohan, Ranga Vemuri
:
Power invariant secure IC design methodology using reduced complementary dynamic and differential logic. VLSI-SoC 2007: 1-6 - [c152]Almitra Pradhan, Ranga Vemuri
:
Regression based circuit matrix models for accurate performance estimation of analog circuits. VLSI-SoC 2007: 48-53 - [c151]Huiying Yang, Ranga Vemuri
:
Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis. VLSI Design 2007: 201-206 - [c150]Balasubramanian Sethuraman, Ranga Vemuri
:
A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures. VLSI Design 2007: 419-426 - [i2]Raoul F. Badaoui, Ranga Vemuri:
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis. CoRR abs/0710.4717 (2007) - [i1]Jawad Khan, Ranga Vemuri:
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms. CoRR abs/0710.4752 (2007) - 2006
- [j22]Nagu R. Dhanwada, Alex Doboli, Adrián Núñez-Aldana, Ranga Vemuri
:
Hierarchical constraint transformation based on genetic optimization for analog system synthesis. Integr. 39(3): 267-290 (2006) - [j21]Jawad Khan, Ranga Vemuri:
Energy management for battery-powered reconfigurable computing platforms. IEEE Trans. Very Large Scale Integr. Syst. 14(2): 135-147 (2006) - [c149]Huiying Yang, Ranga Vemuri:
Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis. DATE 2006: 283-284 - [c148]Balasubramanian Sethuraman, Ranga Vemuri
:
optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs. DATE 2006: 947-952 - [c147]Balasubramanian Sethuraman, Ranga Vemuri
:
Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-Chip. FPL 2006: 1-4 - [c146]Renqiu Huang, Ranga Vemuri
:
Transformation synthesis for data intensive applications to FPGAs. ACM Great Lakes Symposium on VLSI 2006: 349-352 - [c145]Xin Jia, Ranga Vemuri
:
Studying a GALS FPGA architecture using a parameterized automatic design flow. ICCAD 2006: 688-693 - [c144]Mukesh Ranjan, Ranga Vemuri:
Exact hierarchical symbolic analysis of large analog networks using a general interconnection template. ISCAS 2006 - [c143]Vijay Sundaresan, Ranga Vemuri
:
A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning. ISVLSI 2006: 323-328 - [c142]Amitava Bhaduri, Ranga Vemuri
:
Parasitic Aware Routing Methodology Based on Higher Order RLCK Moment Metrics. VLSI Design 2006: 141-146 - [c141]Xin Jia, Ranga Vemuri
:
CAD Tools for a Globally Asynchronous Locally Synchronous FPGA Architecture. VLSI Design 2006: 251-256 - [c140]Mengmeng Ding, Ranga Vemuri
:
Efficient Analog Performance Macromodeling via Sequential Design Space Decomposition. VLSI Design 2006: 553-556 - [c139]Ritochit Chakraborty, Mukesh Ranjan, Ranga Vemuri
:
Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction. VLSI Design 2006: 689-694 - 2005
- [j20]Manish Handa, Ranga Vemuri
:
Hardware assisted two dimensional ultra fast online placement. Int. J. Embed. Syst. 1(3/4): 291-299 (2005) - [c138]Huiying Yang, Mukesh Ranjan, Wim Verhaegen, Mengmeng Ding, Ranga Vemuri
, Georges G. E. Gielen:
Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams. ASP-DAC 2005: 230-235 - [c137]Mengmeng Ding, Glenn Wolfe, Ranga Vemuri:
An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels. ASP-DAC 2005: 477-482 - [c136]Xin Jia, Ranga Vemuri
:
Using GALS architecture to reduce the impact of long wire delay on FPGA performance. ASP-DAC 2005: 1260-1263 - [c135]Mengmeng Ding, Ranga Vemuri:
A combined feasibility and performance macromodel for analog circuits. DAC 2005: 63-68 - [c134]Raoul F. Badaoui, Ranga Vemuri
:
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis. DATE 2005: 138-143 - [c133]Jawad Khan, Ranga Vemuri
:
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms. DATE 2005: 622-627 - [c132]Amitava Bhaduri, Ranga Vemuri
:
Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric. DATE 2005: 922-923 - [c131]Mengmeng Ding, Ranga Vemuri
:
A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling. DATE 2005: 1088-1089 - [c130]Xin Jia, Ranga Vemuri
:
The GAPLA: A Globally Asynchronous Locally Synchronous FPGA Architecture. FCCM 2005: 291-292 - [c129]Xin Jia, Ranga Vemuri
:
A Novel Asynchronous FPGA Architecture Design and Its Performance Evaluation. FPL 2005: 287-292 - [c128]Jawad Khan, Ranga Vemuri
:
Energy Management in Battery-Powered Sensor Networks with Reconfigurable Computing Nodes. FPL 2005: 543-546 - [c127]Renqiu Huang, Ranga Vemuri
:
PAHLS: Towards Run-Time Synthesis for FPGAs. FPL 2005: 739-740 - [c126]Amitava Bhaduri, Ranga Vemuri
:
Moment-driven coupling-aware routing methodology. ACM Great Lakes Symposium on VLSI 2005: 390-395 - [c125]Balasubramanian Sethuraman, Prasun Bhattacharya, Jawad Khan, Ranga Vemuri:
LiPaR: A light-weight parallel router for FPGA-based networks-on-chip. ACM Great Lakes Symposium on VLSI 2005: 452-457 - [c124]Anuradha Agarwal, Glenn Wolfe, Ranga Vemuri
:
Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits. ACM Great Lakes Symposium on VLSI 2005: 482-487 - [c123]Anuradha Agarwal, Ranga Vemuri
:
Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits. ICCAD 2005: 430-436 - [c122]Anuradha Agarwal, Ranga Vemuri
:
Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners. ICCD 2005: 444-452 - [c121]Jawad Khan, Ranga Vemuri
:
Battery-Efficient Task Execution on Reconfigurable Computing Platforms with Multiple Processing Units. IPDPS 2005 - [c120]Raoul F. Badaoui, Ranga Vemuri
:
Analog VLSI circuit-level synthesis using multi-placement structures. ISCAS (6) 2005: 5978-5981 - [c119]Huiying Yang, Anuradha Agarwal, Ranga Vemuri:
Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams. ISVLSI 2005: 71-76 - [c118]Renqiu Huang, Ranga Vemuri:
Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs. ISVLSI 2005: 250-251 - [c117]Mengmeng Ding, Ranga Vemuri:
An Active Learning Scheme Using Support Vector Machines for Analog Circuit Feasibility Classification. VLSI Design 2005: 528-534 - [c116]Madhubanti Mukherjee, Ranga Vemuri
:
On Physical-Aware Synthesis of Vertically Integrated 3D Systems. VLSI Design 2005: 647-652 - [c115]Renqiu Huang, Ranga Vemuri
:
On-Line Synthesis for Partially Reconfigurable FPGAs. VLSI Design 2005: 663-668 - 2004
- [j19]Alex Doboli, Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
:
A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications. ACM Trans. Design Autom. Electr. Syst. 9(2): 238-271 (2004) - [c114]Xin Jia, Ranga Vemuri:
A Design Methodology for Self-Timed Event Logic Pipelines. ESA/VLSI 2004: 475-479 - [c113]Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri:
Fast and accurate parasitic capacitance models for layout-aware. DAC 2004: 145-150 - [c112]Manish Handa, Ranga Vemuri:
An efficient algorithm for finding empty space for online FPGA placement. DAC 2004: 960-965 - [c111]Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri
, Georges G. E. Gielen
:
Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. DATE 2004: 604-609 - [c110]Manish Handa, Ranga Vemuri
:
A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement. DATE 2004: 744-745 - [c109]Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri
:
Accurate Estimation of Parasitic Capacitances in Analog Circuits. DATE 2004: 1364-1365 - [c108]Jawad Khan, Balasubramanian Sethuraman, Ranga Vemuri:
A Power-Performance Trade-off Methodology for Portable Reconfigurable Platforms. ERSA 2004: 33-37 - [c107]Manish Handa, Ranga Vemuri:
Area Fragmentation in Reconfigurable Operating Systems. ERSA 2004: 77-83 - [c106]Jawad Khan, Jayanthi Rajagopalan, Renqiu Huang, Ranga Vemuri:
A Portable Face Recognition System Using Reconfigurable Hardware. ERSA 2004: 213-217 - [c105]Manish Handa, Ranga Vemuri
:
An Integrated Online Scheduling and Placement Methodology. FPL 2004: 444-453 - [c104]Jawad Khan, Ranga Vemuri
:
An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms. FPL 2004: 669-678 - [c103]Xin Jia, Jayanthi Rajagopalan, Ranga Vemuri
:
A Dynamically Reconfigurable Asynchronous FPGA Architecture. FPL 2004: 836-841 - [c102]Renqiu Huang, Manish Handa, Ranga Vemuri
:
Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs. FPL 2004: 900-905 - [c101]Raoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri
:
A high level language for pre-layout extraction in parasite-aware analog circuit synthesis. ACM Great Lakes Symposium on VLSI 2004: 271-276 - [c100]Renqiu Huang, Ranga Vemuri:
Analysis and evaluation of a hybrid interconnect structure for FPGAs. ICCAD 2004: 595-601 - [c99]Ranga Vemuri
, Glenn Wolfe:
Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines. ICCAD 2004: 931-938 - [c98]Madhubanti Mukherjee, Ranga Vemuri
:
Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems. ICCD 2004: 222-227 - [c97]Manish Handa, Ranga Vemuri:
Hardware Assisted Two Dimensional Ultra Fast Placement. IPDPS 2004 - [c96]Renqiu Huang, Ranga Vemuri:
Forward-Looking Macro Generation and Relational Placement During High Level Synthesis to FPGAs. IPDPS 2004 - [c95]Balasubramanian Sethuraman, Jawad Khan, Ranga Vemuri:
Battery-efficient task execution on portable reconfigurable computing. SoCC 2004: 237-240 - 2003
- [j18]Glenn Wolfe, Ranga Vemuri
:
Extraction and use of neural network models in automated synthesis of operational amplifiers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(2): 198-212 (2003) - [j17]Alex Doboli, Ranga Vemuri
:
Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11): 1504-1520 (2003) - [j16]Alex Doboli, Ranga Vemuri
:
Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11): 1556-1568 (2003) - [c94]Madhubanti Mukherjee, Ranga Vemuri:
A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits. ICCD 2003: 436-440 - [c93]Glenn Wolfe, Mengmeng Ding, Ranga Vemuri:
Adaptive Sampling and Modeling of Analog Circuit Performance Parameters. VLSI-SOC 2003: 142- - [c92]Hemanth Sampath, Ranga Vemuri:
MSL: A High-Level Language for Parameterized Analog and Mixed Signal Layout Generators. VLSI-SOC 2003: 416-421 - [c91]Manish Handa, Rajesh Radhakrishnan, Madhubanti Mukherjee, Ranga Vemuri
:
A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs. VLSI Design 2003: 91- - 2002
- [j15]Ranga Vemuri
, Srinivas Katkoori
, Meenakshi Kaul, Jay Roy:
An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications. ACM Trans. Design Autom. Electr. Syst. 7(1): 189-216 (2002) - [j14]Karam S. Chatha, Ranga Vemuri
:
Hardware-software partitioning and pipelined scheduling of transformative applications. IEEE Trans. Very Large Scale Integr. Syst. 10(3): 193-208 (2002) - [c90]Alex Doboli, Ranga Vemuri
:
A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems. DATE 2002: 760-767 - [c89]Jawad Khan, Manish Handa, Ranga Vemuri
:
iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications. FPL 2002: 69-78 - [c88]Srinivasan Dasasathyan, Rajesh Radhakrishnan, Ranga Vemuri
:
Framework for Synthesis of Virtual Pipelines. ASP-DAC/VLSI Design 2002: 326-331 - 2001
- [j13]Naren Narasimhan, Elena Teica, Rajesh Radhakrishnan, Sriram Govindarajan, Ranga Vemuri
:
Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis. Formal Methods Syst. Des. 19(3): 237-273 (2001) - [j12]Ranga Vemuri
, Rajesh K. Gupta:
Guest editorial reconfigurable and adaptive VLSI systems. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 107-108 (2001) - [j11]V. Srinivasan, Sriram Govindarajan, Ranga Vemuri
:
Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 140-158 (2001) - [c87]Sree Ganesan, Ranga Vemuri
:
Analog-Digital Partitioning for Field-Programmable Mixed Signal Systems. ARVLSI 2001: 172-187 - [c86]Rajesh Radhakrishnan, Elena Teica, Ranga Vemuri
:
Verification of Basic Block Schedules Using RTL Transformations. CHARME 2001: 173-178 - [c85]Karam S. Chatha, Ranga Vemuri:
MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs. CODES 2001: 42-47 - [c84]Sree Ganesan, Ranga Vemuri
:
Behavioral Partitioning in the Synthesis of Mixed Analog-Digital Systems. DAC 2001: 133-138 - [c83]Alex Doboli, Ranga Vemuri:
Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints. DAC 2001: 629-634 - [c82]Iyad Ouaiss, Ranga Vemuri
:
Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers. DATE 2001: 650-657 - [c81]Elena Teica, Rajesh Radhakrishnan, Ranga Vemuri
:
On the verification of synthesized designs using automatically generated transformational witnesses. DATE 2001: 798 - [c80]Alex Doboli, Ranga Vemuri:
A regularity-based hierarchical symbolic analysis method for large-scale analog networks. DATE 2001: 806 - [c79]Amit Kasat, Iyad Ouaiss, Ranga Vemuri
:
Memory Synthesis for FPGA-Based Reconfigurable Computers. FPL 2001: 70-80 - [c78]Yi Pan, Jie Li
, Ranga Vemuri
:
Continous Wavelet Transform on Reconfigurable Meshes. IPDPS 2001: 114 - [c77]Iyad Ouaiss, Ranga Vemuri
:
Global memory mapping for FPGA-based reconfigurable systems. IPDPS 2001: 144 - [c76]Alex Doboli, Ranga Vemuri
:
Hierarchical performance optimization for synthesis of linear analog systems. ISCAS (5) 2001: 431-434 - [c75]Sree Ganesan, Ranga Vemuri:
Library Binding for High-Level Synthesis of Analog Systems. VLSI Design 2001: 261-268 - [c74]Sujatha Sundararaman, Sriram Govindarajan, Ranga Vemuri
:
Application Specific Macro Based Synthesis. VLSI Design 2001: 317- - 2000
- [j10]Ranga Vemuri
, Randolph E. Harr:
Configurable Computing: Technology and Applications - Guest Editors' Introduction. Computer 33(4): 39-40 (2000) - [j9]Karam S. Chatha, Ranga Vemuri
:
An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling. Des. Autom. Embed. Syst. 5(3-4): 281-293 (2000) - [j8]Nazanin Mansouri, Ranga Vemuri
:
Automated Correctness Condition Generation for Formal Verification of Synthesized RTL Designs. Formal Methods Syst. Des. 16(1): 59-91 (2000) - [j7]Meenakshi Kaul, Ranga Vemuri
:
Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable Systems. J. VLSI Signal Process. 24(2-3): 181-209 (2000) - [c73]Alex Doboli, Ranga Vemuri
:
Towards a Specification Notation for High-Level Synthesis of Mixed-Signal and Analog Systems. BMAS 2000: 109-116 - [c72]Sree Ganesan, Ranga Vemuri
:
Technology Mapping and Retargeting for Field-Programmable Analog Arrays. DATE 2000: 58-64 - [c71]Satish Ganesan, Ranga Vemuri
:
An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement. DATE 2000: 320-325 - [c70]Iyad Ouaiss, Ranga Vemuri
:
Efficient Resource Arbitration in Reconfigurable Computing Environments. DATE 2000: 560-566 - [c69]Sriram Govindarajan, Ranga Vemuri
:
Improving the Schedule Quality of Static-List Time-Constrained Scheduling. DATE 2000: 749 - [c68]Sriram Govindarajan, Ranga Vemuri
:
Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS. FPL 2000: 7-18 - [c67]Rajesh Radhakrishnan, Elena Teica, Ranga Vemuri:
An approach to high-level synthesis system validation using formally verified transformations. HLDVT 2000: 80-85 - [c66]Preetham Lakshmikanthan, Sriram Govindarajan, Vinoo Srinivasan, Ranga Vemuri
:
Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints. IPDPS Workshops 2000: 924-931 - [c65]Srinivas Katkoori
, Ranga Vemuri
:
Scheduling for low power under resource and latency constraints. ISCAS 2000: 53-56 - [c64]Alex Doboli, Nagu R. Dhanwada, Ranga Vemuri
:
A heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems. ISCAS 2000: 181-184 - [c63]Abhijit Ghosh, Ranga Vemuri:
Formal Verification of Synthesized Mixed Signal Designs Using *BMDs. VLSI Design 2000: 84- - [c62]Sriram Govindarajan, Vinoo Srinivasan, Preetham Lakshmikanthan, Ranga Vemuri:
A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures. VLSI Design 2000: 212-219
1990 – 1999
- 1999
- [c61]Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
:
Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis. ASP-DAC 1999: 153-156 - [c60]Meenakshi Kaul, Ranga Vemuri
, Sriram Govindarajan, Iyad Ouaiss:
An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications. DAC 1999: 616-622 - [c59]Alex Doboli, Adrián Núñez-Aldana, Nagu R. Dhanwada, Sree Ganesan, Ranga Vemuri
:
Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration. DAC 1999: 951-957 - [c58]Meenakshi Kaul, Ranga Vemuri
:
Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs. DATE 1999: 202-209 - [c57]Nazanin Mansouri, Ranga Vemuri
:
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs. DATE 1999: 223- - [c56]Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
:
Hierarchical Constraint Transformation Using Directed Interval Search for Analog System Synthesis. DATE 1999: 328- - [c55]Alex Doboli, Ranga Vemuri
:
A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems. DATE 1999: 338-345 - [c54]Adrián Núñez-Aldana, Ranga Vemuri
:
An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis. DATE 1999: 406-411 - [c53]Vinoo Srinivasan, Ranga Vemuri:
Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures. FCCM 1999: 272- - [c52]Vinoo Srinivasan, Ranga Vemuri:
Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures. FPGA 1999: 253 - [c51]Karam S. Chatha, Ranga Vemuri
:
Hardware-Software Codesign for Dynamically Reconfigurable Architectures. FPL 1999: 175-184 - [c50]Abhijit Ghosh, Sandeep K. Lodha, Ranga Vemuri:
Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops. Great Lakes Symposium on VLSI 1999: 140-143 - [c49]Srinivas Katkoori
, Ranga Vemuri:
Accurate Resource Estimation Algorithms for Behavioral Synthesis. Great Lakes Symposium on VLSI 1999: 338-339 - [c48]Abhijit Ghosh, Ranga Vemuri:
Formal Verification of Synthesized Analog Designs. ICCD 1999: 40-45 - [c47]Sree Ganesan, Ranga Vemuri:
A Methodology for Rapid Prototyping of Analog Systems. ICCD 1999: 482-488 - [c46]Alex Doboli, Ranga Vemuri:
A Decomposition-based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications. VLSI 1999: 305-317 - [c45]Adrián Núñez-Aldana, Ranga Vemuri:
A Linear Programming Approach for Synthesis of Mixed-Signal Interface Elements. VLSI 1999: 318-32 - [c44]Vinoo Srinivasan, Shankar Radhakrishnan, Ranga Vemuri
, Jeffrey Walrath:
Interconnect Synthesis for Reconfigurable Multi-FPGA Architectures. IPPS/SPDP Workshops 1999: 588-596 - [c43]Meenakshi Kaul, Ranga Vemuri
:
Integrated Block-Processing and Design-Space Exploration in Temporal Partitioning for RTR Architectures. IPPS/SPDP Workshops 1999: 606-615 - [c42]Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri:
A genetic approach to simultaneous parameter space exploration and constraint transformation in analog synthesis. ISCAS (6) 1999: 362-365 - [c41]Karam S. Chatha, Ranga Vemuri:
An Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW Systems. IEEE International Workshop on Rapid System Prototyping 1999: 134-139 - [c40]Sree Ganesan, Ranga Vemuri:
FAAR: A Router for Field-Programmable Analog Arrays. VLSI Design 1999: 556-563 - [c39]Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri
:
Component Characterization and Constraint Transformation Based on Directed Intervals for Analog Synthesis. VLSI Design 1999: 589-596 - 1998
- [j6]Srinivas Katkoori
, Ranga Vemuri
:
Architectural Power Estimation Based on Behavior Level Profiling. VLSI Design 7(3): 255-270 (1998) - [c38]Karam S. Chatha, Ranga Vemuri:
RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns. CODES 1998: 139-143 - [c37]Vinoo Srinivasan, Shankar Radhakrishnan, Ranga Vemuri
:
Hardware Software Partitioning with Integrated Hardware Design Space Exploration. DATE 1998: 28-35 - [c36]Meenakshi Kaul, Ranga Vemuri
:
Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures. DATE 1998: 389-396 - [c35]Sriram Govindarajan, Iyad Ouaiss, Meenakshi Kaul, Vinoo Srinivasan, Ranga Vemuri
:
An Effective Design System for Dynamically Reconfigurable Architectures. FCCM 1998: 312-313 - [c34]Nazanin Mansouri, Ranga Vemuri:
A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool. FMCAD 1998: 204-221 - [c33]Viresh Paruthi, Nazanin Mansouri, Ranga Vemuri:
Automatic data path abstraction for verification of large scale designs. ICCD 1998: 192-194 - [c32]Naren Narasimhan, Elena Teica, Rajesh Radhakrishnan, Sriram Govindarajan, Ranga Vemuri:
Theorem proving guided development of formal assertions in a resource-constrained scheduler for high-level synthesis. ICCD 1998: 392-399 - [c31]Jeffrey Walrath, Ranga Vemuri
:
A Performance Modeling and Analysis Environment for Reconfigurable Computers. IPPS/SPDP Workshops 1998: 19-24 - [c30]Iyad Ouaiss, Sriram Govindarajan, Vinoo Srinivasan, Meenakshi Kaul, Ranga Vemuri
:
An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures. IPPS/SPDP Workshops 1998: 31-36 - [c29]Karam S. Chatha, Ranga Vemuri
:
A Tool for Partitioning and Pipelined Scheduling of Hardware-Software Systems. ISSS 1998: 145-151 - [c28]Karam S. Chatha, Ranga Vemuri:
Performance Evaluation Tool for Rapid Prototyping of Hardware-Software Codesigns. International Workshop on Rapid System Prototyping 1998: 218-224 - [c27]Naren Narasimhan, Ranga Vemuri
:
On the Effectiveness of Theorem Proving Guided Discovery of Formal Assertions for a Register Allocator in a High-Level Synthesis System. TPHOLs 1998: 367-386 - [c26]Nagu R. Dhanwada, Ranga Vemuri:
Constraint Allocation in Analog System Synthesis. VLSI Design 1998: 253-258 - [c25]Vinoo Srinivasan, Ranga Vemuri:
A Retiming Based Relaxation Heuristic for Resource-Constrained Loop Pipelining. VLSI Design 1998: 435-441 - 1997
- [c24]Natesan Venkateswaran, Anurag Gupta, Srinivas Katkoori
, Dinesh Bhatia, Ranga Vemuri:
A constructive method for data path area estimation during high-level VLSI synthesis. ASP-DAC 1997: 509-515 - [c23]Jeffrey Walrath, Ranga Vemuri
:
Symbolic Evaluation of Performance Models for Tradeoff Visualization. DAC 1997: 359-364 - [c22]Sriram Govindarajan, Ranga Vemuri
:
Cone-based clustering heuristic for list-scheduling algorithms. ED&TC 1997: 456-462 - [c21]Jeffrey Walrath, Ranga Vemuri
, W. Bradley:
Performance verification using partial evaluation and interval analysis. ED&TC 1997: 622 - [c20]Sriram Govindarajan, Ranga Vemuri:
Dynamic Bounding of Successor Force Computations in the Force Directed List Scheduling Algorithms. ICCD 1997: 752-757 - [c19]Madhavi Vootukuru, Ranga Vemuri, Nand Kumar:
Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA Designs. VLSI Design 1997: 140-145 - 1996
- [j5]Ranga Vemuri
, Ram Manday, Vijay Meduri:
Performance Modeling Using PDL. Computer 29(4): 44-53 (1996) - [c18]Naren Narasimhan, Vinoo Srinivasan, Madhavi Vootukuru, Jeffrey Walrath, Sriram Govindarajan, Ranga Vemuri:
Rapid Prototyping of Reconfigurable Coprocessors. ASAP 1996: 303-312 - [c17]Vinoo Srinivasan, Nand Kumar, Ranga Vemuri:
Hierarchical behavioral partitioning for multicomponent synthesis. EURO-DAC 1996: 212-217 - [c16]Naren Narasimhan, Ranga Vemuri
:
Specification of Control Flow Properties for Verification of Synthesized VHDL Designs. FMCAD 1996: 327-345 - [c15]Srinivas Katkoori
, Ranga Vemuri:
Simulation based architectural power estimation for PLA-based controllers. ISLPED 1996: 121-124 - [c14]Srinivas Katkoori
, Ranga Vemuri, Jay Roy:
A Hierarchical Register Optimization Algorithm for Behavioral Synthesis. VLSI Design 1996: 126-132 - [c13]Naren Narasimhan, Ranga Vemuri, Jay Roy:
Synchronous Controller Models for Synthesis from Communicating VHDL Processes. VLSI Design 1996: 198-204 - 1995
- [j4]Nand Kumar, Srinivas Katkoori
, Leo Rader, Ranga Vemuri
:
Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems. IEEE Des. Test Comput. 12(3): 70-84 (1995) - [j3]Ranga Vemuri
, R. Kalyanaraman:
Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming. IEEE Trans. Very Large Scale Integr. Syst. 3(2): 201-214 (1995) - [c12]Srinivas Katkoori
, Nand Kumar, Ranga Vemuri:
High level profiling based low power synthesis technique. ICCD 1995: 446-453 - [c11]William L. Bradley, Ranga Vemuri:
Transformations for functional verification of synthesized designs. VLSI Design 1995: 243-248 - 1993
- [j2]Ranga Vemuri, Nand Kumar, Raghu Vutukuru, Prasad Subba Rao, Praveen Sinha, Ning Ren, Paddy Mamtora, Ram Mandayam, Ram Vemuri, Jayanta Roy:
An Integrated Multicomponent Synthesis for MCMs. Computer 26(4): 62-74 (1993) - [c10]Ram Mandayam, Ranga Vemuri:
Performance Specification and Measurement. CHDL 1993: 281-298 - [c9]Ranga Vemuri, Paddy Mamtora, Praveen Sinha, Nand Kumar, Jayanta Roy, Raghu Vutukuru:
Experiences in Functional Validation of a High Level Synthesis System. DAC 1993: 194-201 - [c8]Ram Mandayam, Ranga Vemuri
:
Performance Specification Using Attributed Grammars. DAC 1993: 661-667 - 1992
- [j1]Jayanta Roy, Nand Kumar, Rajiv Dutta, Ranga Vemuri
:
DSS: A Distributed High-Level Synthesis System. IEEE Des. Test Comput. 9(2): 18-32 (1992) - [c7]Rajiv Dutta, Jayanta Roy, Ranga Vemuri:
Distributed Design-Space Exploration for High-Level Synthesis Systems. DAC 1992: 644-650 - [c6]Nand Kumar, Ranga Vemuri:
Finite state machine verification on MIMD machines. EURO-DAC 1992: 514-520 - 1991
- [c5]Ranga Vemuri
, Anuradha Sridhar:
Temporal Precondition Verification of Design Transformations. CAV 1991: 125-135 - [c4]Ram Vemuri, Ranga Vemuri:
Genetic synthesis: performance-driven logic synthesis using genetic evolution. Great Lakes Symposium on VLSI 1991: 312-317 - 1990
- [c3]Ranga Vemuri
:
On the notion of the normal form register-level structures and its applications in design-space exploration. EURO-DAC 1990: 46-51
1980 – 1989
- 1986
- [c2]Cris Koutsougeras, Christos A. Papachristou
, Ranga Vemuri
:
Data flow graph partitioning to reduce communication cost. MICRO 1986: 82-91
1970 – 1979
- 1978
- [c1]Ranga Vemuri, J. V. Cornacchio:
Continuing education in microprocessors: Use of software simulators. COMPSAC 1978: 803-806
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