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2020 – today
- 2024
[j248]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 40(1): 1-2 (2024)- [j247]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 40(2): 137-138 (2024) - [j246]Soham Roy
, Spencer K. Millican, Vishwani D. Agrawal:
A Survey and Recent Advances: Machine Intelligence in Electronic Testing. J. Electron. Test. 40(2): 139-158 (2024) - [j245]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 40(3): 289 (2024) - [j244]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 40(4): 417-418 (2024) - [c227]Soham Roy, Vishwani D. Agrawal:
An Amalgamated Testability Measure Derived from Machine Intelligence. VLSID 2024: 696-701 - 2023
- [j243]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 39(1): 1-2 (2023) - [j242]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 39(2): 123 (2023) - [j241]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 39(3): 263-264 (2023) - [j240]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 39(4): 403-404 (2023) - [j239]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 39(5): 535-536 (2023) - 2022
- [j238]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 38(1): 1-2 (2022) - [j237]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 38(2): 125-126 (2022) - [j236]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 38(3): 231 (2022) - [j235]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 38(4): 335-336 (2022) - [j234]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 38(5): 463-464 (2022) - [j233]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 38(6): 575 (2022) - [c226]Ziqi Zhou, Ujjwal Guin, Peng Li, Vishwani D. Agrawal:
Fault Modeling and Test Generation for Technology-Specific Defects of Skyrmion Logic Circuits. VTS 2022: 1-7 - 2021
- [j232]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 37(1): 1-2 (2021) - [j231]Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal:
Estimating Operational Age of an Integrated Circuit. J. Electron. Test. 37(1): 25-40 (2021) - [j230]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 37(2): 157-158 (2021) - [j229]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 37(3): 285-286 (2021) - [j228]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 37(4): 423-424 (2021) - [j227]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 37(5): 569-570 (2021) - [c225]Soham Roy, Spencer K. Millican, Vishwani D. Agrawal:
Unsupervised Learning in Test Generation for Digital Integrated Circuits. ETS 2021: 1-4 - [c224]Soham Roy, Spencer K. Millican, Vishwani D. Agrawal:
Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator. VLSID 2021: 316-321 - [c223]Soham Roy, Spencer K. Millican, Vishwani D. Agrawal:
Special Session - Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits. VTS 2021: 1-14 - [c222]Ziqi Zhou, Ujjwal Guin, Peng Li, Vishwani D. Agrawal:
Defect Characterization and Testing of Skyrmion-Based Logic Circuits. VTS 2021: 1-7 - 2020
- [j226]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 36(1): 1-2 (2020) - [j225]Soham Roy, Brandon Stiene, Spencer K. Millican, Vishwani D. Agrawal:
Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures. J. Electron. Test. 36(1): 123-133 (2020) - [j224]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 36(2): 143-144 (2020) - [j223]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 36(3): 297-298 (2020) - [j222]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 36(4): 439-440 (2020) - [j221]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 36(5): 565-566 (2020) - [j220]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 36(6): 677-678 (2020) - [c221]Soham Roy, Spencer K. Millican, Vishwani D. Agrawal:
Machine Intelligence for Efficient Test Pattern Generation. ITC 2020: 1-5 - [c220]Vishwani D. Agrawal:
Message from the Steering Committee Chair. VLSID 2020: i - [c219]Yang Sun, Spencer K. Millican, Vishwani D. Agrawal:
Special Session: Survey of Test Point Insertion for Logic Built-in Self-test. VTS 2020: 1-6
2010 – 2019
- 2019
- [j219]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 35(1): 1-2 (2019) - [j218]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 35(2): 127-128 (2019) - [j217]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 35(3): 269-270 (2019) - [j216]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 35(4): 421-422 (2019) - [j215]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 35(5): 573 (2019) - [j214]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 35(6): 761-763 (2019) - [c218]Spencer K. Millican, Yang Sun, Soham Roy, Vishwani D. Agrawal:
Applying Neural Networks to Delay Fault Testing: Test Point Insertion and Random Circuit Training. ATS 2019: 13-18 - [c217]Soham Roy, Brandon Stiene, Spencer K. Millican, Vishwani D. Agrawal:
Improved Random Pattern Delay Fault Coverage Using Inversion Test Points. NATW 2019: 1-6 - [c216]Harshil Goyal, Vishwani D. Agrawal:
Technology Characterization Model and Scaling for Energy Management. VDAT 2019: 679-693 - [c215]Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal:
Two-Pattern ∆IDDQ Test for Recycled IC Detection. VLSID 2019: 82-87 - [c214]Mustafa M. Shihab, Vishwani D. Agrawal:
Energy Efficient Power Distribution on Many-Core SoC. VLSID 2019: 488-493 - [c213]Jubayer Mahmod, Spencer K. Millican, Ujjwal Guin, Vishwani D. Agrawal:
Special Session: Delay Fault Testing - Present and Future. VTS 2019: 1-10 - 2018
- [j213]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 34(1): 1 (2018) - [j212]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 34(2): 105 (2018) - [j211]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 34(3): 209 (2018) - [j210]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 34(4): 371-372 (2018) - [j209]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 34(5): 507-508 (2018) - [j208]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 34(6): 615-617 (2018) - [c212]Ziqi Zhou, Ujjwal Guin, Vishwani D. Agrawal:
Modeling and test generation for combinational hardware Trojans. VTS 2018: 1-6 - 2017
- [j207]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 33(1): 1-3 (2017) - [j206]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 33(2): 141 (2017) - [j205]Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal:
Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling. J. Electron. Test. 33(2): 171-187 (2017) - [j204]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 33(3): 275 (2017) - [j203]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 33(4): 377-378 (2017) - [j202]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 33(5): 539-540 (2017) - [j201]Bei Zhang, Vishwani D. Agrawal:
Three-Stage Optimization of Pre-Bond Diagnosis of TSV Defects. J. Electron. Test. 33(5): 573-589 (2017) - [j200]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 33(6): 689-690 (2017) - 2016
- [j199]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 32(1): 1-2 (2016) - [j198]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 32(2): 107-108 (2016) - [j197]Baohu Li, Vishwani D. Agrawal:
Applications of Mixed-Signal Technology in Digital Testing. J. Electron. Test. 32(2): 209-225 (2016) - [j196]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 32(3): 241-242 (2016) - [j195]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 32(4): 399 (2016) - [j194]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 32(5): 505-506 (2016) - [j193]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 32(6): 653-654 (2016) - [c211]Muralidharan Venkatasubramanian, Vishwani D. Agrawal:
Failures Guide Probabilistic Search for a Hard-to-Find Test. NATW 2016: 18-23 - [c210]Muralidharan Venkatasubramanian, Vishwani D. Agrawal:
Database Search and ATPG - Interdisciplinary Domains and Algorithms. VLSID 2016: 38-43 - 2015
- [j192]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 31(1): 1-2 (2015) - [j191]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 31(2): 123 (2015) - [j190]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 31(3): 225 (2015) - [j189]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 31(4): 335 (2015) - [j188]Sindhu Gunasekar, Vishwani D. Agrawal:
A Maximum Power Algorithm to Find Frequencies for Aperiodic Clock Testing. J. Electron. Test. 31(4): 403-410 (2015) - [j187]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 31(5-6): 421-422 (2015) - [j186]Suraj Sindia, Vishwani D. Agrawal:
Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests. J. Electron. Test. 31(5-6): 479-489 (2015) - [c209]Hejia Liu, Vishwani D. Agrawal:
Securing IEEE 1687-2014 Standard Instrumentation Access by LFSR Key. ATS 2015: 91-96 - [c208]Muralidharan Venkatasubramanian, Vishwani D. Agrawal, James J. Janaher:
Quest for a quantum search algorithm for testing stuck-at faults in digital circuits. DFTS 2015: 127-132 - [c207]Víctor H. Champac, Yervant Zorian, Letícia Maria Bolzani Pöhls, Vishwani D. Agrawal:
Message from the LATS2015 Chairs. LATS 2015: 1 - [c206]Baohu Li, Bei Zhang, Vishwani D. Agrawal:
Adopting multi-valued logic for reduced pin-count testing. LATS 2015: 1-6 - [c205]Harshit Goyal, Vishwani D. Agrawal:
Characterizing Processors for Energy and Performance Management. MTV 2015: 67-72 - [c204]Baohu Li, Vishwani D. Agrawal:
Multivalued Logic for Reduced Pin Count and Multi-site SoC Testing. NATW 2015: 49-54 - [c203]Huiting Zhang, Vishwani D. Agrawal:
SoC TAM Design to Minimize Test Application Time. NATW 2015: 55-60 - [c202]Bei Zhang, Vishwani D. Agrawal:
Diagnostic Tests for Pre-bond TSV Defects. VLSID 2015: 387-392 - [c201]Sindhu Gunasekar, Vishwani D. Agrawal:
Few Good Frequencies for Power-Constrained Test. VLSID 2015: 393-398 - 2014
- [j185]Bei Zhang, Vishwani D. Agrawal:
A Novel Wafer Manipulation Method for Yield Improvement and Cost Reduction of 3D Wafer-on-Wafer Stacked ICs. J. Electron. Test. 30(1): 57-75 (2014) - [j184]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 30(2): 155-156 (2014) - [j183]Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal:
A Test Time Theorem and its Applications. J. Electron. Test. 30(2): 229-236 (2014) - [j182]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 30(3): 251-252 (2014) - [j181]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 30(4): 383-384 (2014) - [j180]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 30(5): 491-492 (2014) - [j179]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 30(6): 637-638 (2014) - [j178]Yu Zhang, Bei Zhang, Vishwani D. Agrawal:
Diagnostic Test Generation for Transition Delay Faults Using Stuck-At Fault Detection Tools. J. Electron. Test. 30(6): 763-780 (2014) - [j177]Karthik Naishathrala Jayaraman, Vishwani D. Agrawal:
A Four-Transistor Level Converter for Dual-Voltage Low-Power Design. J. Low Power Electron. 10(4): 617-628 (2014) - [c200]Bei Zhang, Vishwani D. Agrawal:
An optimized diagnostic procedure for pre-bond TSV defects. ICCD 2014: 189-194 - [c199]Suraj Sindia, Vishwani D. Agrawal:
Specification test minimization for given defect level. LATW 2014: 1-6 - [c198]Sindhu Gunasekar, Vishwani D. Agrawal:
Optimal Selection of ATE Frequencies for Test Time Reduction Using Aperiodic Clock. NATW 2014: 52-56 - [c197]Muralidharan Venkatasubramanian, Vishwani D. Agrawal:
A New Test Vector Search Algorithm for a Single Stuck-at Fault Using Probabilistic Correlation. NATW 2014: 57-60 - 2013
- [j176]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 29(1): 1-2 (2013) - [j175]Ozgur Sinanoglu, Vishwani D. Agrawal:
Eliminating the Timing Penalty of Scan. J. Electron. Test. 29(1): 103-114 (2013) - [j174]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 29(2): 121 (2013) - [j173]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 29(3): 255 (2013) - [j172]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 29(4): 453 (2013) - [j171]Suraj Sindia, Vishwani D. Agrawal:
Neural Network Guided Spatial Fault Resilience in Array Processors. J. Electron. Test. 29(4): 473-483 (2013) - [j170]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 29(5): 617 (2013) - [j169]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 29(6): 741-742 (2013) - [j168]Mridula Allani, Vishwani D. Agrawal:
Energy-Efficient Dual-Voltage Design Using Topological Constraints. J. Low Power Electron. 9(3): 275-287 (2013) - [c196]Bei Zhang, Baohu Li, Vishwani D. Agrawal:
Yield analysis of a novel wafer manipulation method in 3D stacking. 3DIC 2013: 1-8 - [c195]Suraj Sindia, Vishwani D. Agrawal:
High sensitivity test signatures for unconventional analog circuit test paradigms. ITC 2013: 1-10 - [c194]Praveen Venkataramani, Vishwani D. Agrawal:
ATE test time reduction using asynchronous clock period. ITC 2013: 1-10 - [c193]Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal:
A test time theorem and its applications. LATW 2013: 1-5 - [c192]Chidambaram Alagappan, Vishwani D. Agrawal:
Defect Diagnosis of Digital Circuits Using Surrogate Faults. VDAT 2013: 376-386 - [c191]Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal:
Power-aware SoC test optimization through dynamic voltage and frequency scaling. VLSI-SoC 2013: 102-107 - [c190]Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal:
Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages. VLSI Design 2013: 267-272 - [c189]Praveen Venkataramani, Vishwani D. Agrawal:
Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage. VLSI Design 2013: 273-278 - [c188]Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal:
Finding best voltage and frequency to shorten power-constrained test time. VTS 2013: 1-6 - 2012
- [j167]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 28(1): 1 (2012) - [j166]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 28(2): 151-152 (2012) - [j165]Mohammed Ashfaq Shukoor, Vishwani D. Agrawal:
Diagnostic Test Set Minimization and Full-Response Fault Dictionary. J. Electron. Test. 28(2): 177-187 (2012) - [j164]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 28(3): 263-264 (2012) - [j163]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 28(4): 389-390 (2012) - [j162]Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing. J. Electron. Test. 28(4): 541-549 (2012) - [j161]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 28(5): 551-552 (2012) - [j160]Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients. J. Electron. Test. 28(5): 757-771 (2012) - [j159]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 28(6): 773-774 (2012) - [j158]Kanad Chakraborty, Vishwani D. Agrawal:
Data-Driven DPPM Estimation and Adaptive Fault Coverage Calibration Using MATLAB®. J. Electron. Test. 28(6): 869-875 (2012) - [c187]Suraj Sindia, Vishwani D. Agrawal:
Tailoring Tests for Functional Binning of Integrated Circuits. Asian Test Symposium 2012: 95-100 - [c186]Suraj Sindia, Fa Foster Dai, Vishwani D. Agrawal, Virendra Singh:
Impact of process variations on computers used for image processing. ISCAS 2012: 1444-1447 - [c185]Ozgur Sinanoglu, Vishwani D. Agrawal:
Retiming scan circuit to eliminate timing penalty. LATW 2012: 1-6 - [c184]Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal:
Optimal power-constrained SoC test schedules with customizable clock rates. SoCC 2012: 271-276 - [c183]Farhana Rashid, Vishwani D. Agrawal:
Power Problems in VLSI Circuit Testing. VDAT 2012: 393-405 - [c182]Vishwani D. Agrawal:
Keynote Talk: A History of the VLSI Design Conference. VLSI Design 2012: 1-2 - [c181]Priyadharshini Shanmugasundaram, Vishwani D. Agrawal:
Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock. VLSI Design 2012: 448-453 - [c180]Lixing Zhao, Vishwani D. Agrawal:
Net diagnosis using stuck-at and transition fault models. VTS 2012: 221-226 - [c179]Suraj Sindia, Vishwani D. Agrawal:
Towards spatial fault resilience in array processors. VTS 2012: 288-293 - [e1]Vishwani D. Agrawal, Srimat T. Chakradhar:
25th International Conference on VLSI Design, Hyderabad, India, January 7-11, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-0438-2 [contents] - 2011
- [j157]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 27(1): 1-2 (2011) - [j156]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 27(2): 95 (2011) - [j155]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 27(3): 219 (2011) - [j154]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 27(4): 425-426 (2011) - [j153]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 27(5): 579 (2011) - [j152]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 27(6): 681-682 (2011) - [j151]Kyungseok Kim, Vishwani D. Agrawal:
Ultra Low Energy CMOS Logic Using Below-Threshold Dual-Voltage Supply. J. Low Power Electron. 7(4): 460-470 (2011) - [c178]Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
Test and Diagnosis of Analog Circuits Using Moment Generating Functions. Asian Test Symposium 2011: 371-376 - [c177]Yu Zhang, Vishwani D. Agrawal:
Reduced complexity test generation algorithms for transition fault diagnosis. ICCD 2011: 96-101 - [c176]Kyungseok Kim, Vishwani D. Agrawal:
Minimum energy CMOS design with dual subthreshold supply and multiple logic-level gates. ISQED 2011: 689-694 - [c175]Vishwani D. Agrawal:
Testing for faults, looking for defects. LATW 2011: 1 - [c174]Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
Testing linear and non-linear analog circuits using moment generating functions. LATW 2011: 1-6 - [c173]Kyungseok Kim, Vishwani D. Agrawal:
True Minimum Energy Design Using Dual Below-Threshold Supply Voltages. VLSI Design 2011: 292-297 - [c172]Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients. VTS 2011: 64-69 - [c171]Priyadharshini Shanmugasundaram, Vishwani D. Agrawal:
Dynamic scan clock control for test time reduction maintaining peak power limit. VTS 2011: 248-253 - [c170]Srinivasulu Alampally, R. T. Venkatesh, Priyadharshini Shanmugasundaram, Rubin A. Parekhji, Vishwani D. Agrawal:
An efficient test data reduction technique through dynamic pattern mixing across multiple fault models. VTS 2011: 285-290 - 2010
- [j150]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 26(1): 1-2 (2010) - [j149]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 26(2): 145 (2010) - [j148]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 26(3): 293 (2010) - [j147]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 26(4): 401 (2010) - [j146]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 26(5): 495 (2010) - [j145]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 26(6): 595-596 (2010) - [c169]Yu Zhang, Vishwani D. Agrawal:
A diagnostic test generation system and a coverage metric. ETS 2010: 254 - [c168]Fan Wang, Vishwani D. Agrawal:
Soft error rate determination for nanoscale sequential logic. ISQED 2010: 225-230 - [c167]Yu Zhang, Vishwani D. Agrawal:
A diagnostic test generation system. ITC 2010: 360-368 - [c166]Yu Zhang, Vishwani D. Agrawal:
An algorithm for diagnostic fault simulation. LATW 2010: 1-5 - [c165]Suraj Sindia, Virendra Singh, Vishwani D. Agrawal:
Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients. VLSI Design 2010: 288-293 - [c164]Nitin Yogi, Vishwani D. Agrawal:
Application of signal and noise theory to digital VLSI testing. VTS 2010: 215-220
2000 – 2009
- 2009
- [j144]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 25(1): 1 (2009) - [j143]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 25(4-5): 209 (2009) - [j142]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 25(6): 285 (2009) - [j141]Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
Variable Input Delay CMOS Logic for Low Power Design. IEEE Trans. Very Large Scale Integr. Syst. 17(10): 1534-1545 (2009) - [c163]Suraj Sindia, Virendra Singh, Vishwani D. Agrawal:
Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients. Asian Test Symposium 2009: 63-68 - [c162]Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal:
On Minimization of Peak Power for Scan Circuit during Test. ETS 2009: 25-30 - [c161]Mohammed Ashfaq Shukoor, Vishwani D. Agrawal:
A Two Phase Approach for Minimal Diagnostic Test Set Generation. ETS 2009: 115-120 - [c160]Suraj Sindia, Virendra Singh, Vishwani D. Agrawal:
Polynomial coefficient based DC testing of non-linear analog circuits. ACM Great Lakes Symposium on VLSI 2009: 69-74 - [c159]Wei Jiang, Vishwani D. Agrawal:
Designing Variation-tolerance in Mixed-signal Components of a System-on-chip. ISCAS 2009: 2313-2316 - [c158]Jins D. Alexander, Vishwani D. Agrawal:
Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations. ISVLSI 2009: 127-132 - [c157]Fan Wang, Vishwani D. Agrawal:
Soft Error Rates with Inertial and Logical Masking. VLSI Design 2009: 459-464 - [c156]Sreekumar Menon, Adit D. Singh, Vishwani D. Agrawal:
Output Hazard-Free Transition Delay Fault Test Generation. VTS 2009: 97-102 - 2008
- [j140]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 24(1-3): 1 (2008) - [j139]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 24(4): 321 (2008) - [j138]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 24(5): 421 (2008) - [j137]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 24(6): 505-506 (2008) - [c155]Nitin Yogi, Vishwani D. Agrawal:
Sequential Circuit BIST Synthesis Using Spectrum and Noise from ATPG Patterns. ATS 2008: 69-74 - [c154]Vishwani D. Agrawal:
A tutorial on test power. ISLPED 2008: 237-238 - [c153]Wei Jiang, Vishwani D. Agrawal:
Built-in Self-Calibration of On-chip DAC and ADC. ITC 2008: 1-10 - [c152]Fan Wang, Vishwani D. Agrawal:
Single Event Upset: An Embedded Tutorial. VLSI Design 2008: 429-434 - [c151]Yuanlin Lu, Vishwani D. Agrawal:
Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation. VLSI Design 2008: 527-532 - [c150]Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal:
Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. VTS 2008: 329-335 - 2007
- [j136]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 23(1): 5 (2007) - [j135]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 23(2-3): 111 (2007) - [j134]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 23(5): 369 (2007) - [j133]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 23(6): 465 (2007) - [j132]Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal:
Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. IEEE Trans. Very Large Scale Integr. Syst. 15(11): 1245-1255 (2007) - [c149]Soumitra Bose, Vishwani D. Agrawal:
Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis. ITC 2007: 1-10 - [c148]Soumitra Bose, Hillary Grimes, Vishwani D. Agrawal:
Delay fault simulation with bounded gate delay mode. ITC 2007: 1-10 - [c147]Omar I. Khan, Michael L. Bushnell, Suresh Kumar Devanathan, Vishwani D. Agrawal:
SPARTAN: a spectral and information theoretic approach to partial-scan. ITC 2007: 1-10 - [c146]Yuanlin Lu, Vishwani D. Agrawal:
Statistical Leakage and Timing Optimization for Submicron Process Variation. VLSI Design 2007: 439-444 - [c145]Nitin Yogi, Vishwani D. Agrawal:
Spectral RTL Test Generation for Microprocessors. VLSI Design 2007: 473-478 - [c144]Kalyana R. Kantipudi, Vishwani D. Agrawal:
A Reduced Complexity Algorithm for Minimizing N-Detect Tests. VLSI Design 2007: 492-497 - [c143]Soumitra Bose, Vishwani D. Agrawal:
Delay Test Quality Evaluation Using Bounded Gate Delays. VTS 2007: 23-28 - 2006
- [j131]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 22(1): 5 (2006) - [j130]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 22(2): 111 (2006) - [j129]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 22(4-6): 307 (2006) - [j128]Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
Transistor Sizing of Logic Gates to Maximize Input Delay Variability. J. Low Power Electron. 2(1): 121-128 (2006) - [j127]Yuanlin Lu, Vishwani D. Agrawal:
CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff. J. Low Power Electron. 2(3): 378-387 (2006) - [c142]Nitin Yogi, Vishwani D. Agrawal:
Spectral RTL Test Generation for Gate-Level Stuck-at Faults. ATS 2006: 83-88 - [c141]Fei Hu, Vishwani D. Agrawal:
Input-specific dynamic power optimization for VLSI circuits. ISLPED 2006: 232-237 - [c140]Soumitra Bose, Vishwani D. Agrawal:
Fault Coverage Estimation for Non-Random Functional Input Sequences. ITC 2006: 1-10 - [c139]Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram:
Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring. VTS 2006: 88-93 - 2005
- [j126]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 21(1): 5 (2005) - [j125]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 21(2): 111 (2005) - [j124]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 21(3): 199 (2005) - [j123]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 21(5): 459 (2005) - [j122]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 21(6): 567 (2005) - [j121]Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja:
Combinational automatic test pattern generation for acyclic sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(6): 948-956 (2005) - [c138]Vishwani D. Agrawal, Alok S. Doshi:
Concurrent Test Generation. Asian Test Symposium 2005: 294-299 - [c137]Raja K. K. R. Sandireddy, Vishwani D. Agrawal:
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits. DATE 2005: 1014-1019 - [c136]Fei Hu, Vishwani D. Agrawal:
Dual-transition glitch filtering in probabilistic waveform power estimation. ACM Great Lakes Symposium on VLSI 2005: 357-360 - [c135]Fei Hu, Vishwani D. Agrawal:
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis. ICCD 2005: 366-372 - [c134]Anand S. Mudlapur, Vishwani D. Agrawal, Adit D. Singh:
A random access scans architecture to reduce hardware overhead. ITC 2005: 9 - [c133]Yuanlin Lu, Vishwani D. Agrawal:
Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing. PATMOS 2005: 217-226 - [c132]Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
Design of Variable Input Delay Gates for Low Dynamic Power Circuits. PATMOS 2005: 436-445 - [c131]Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
Variable Input Delay CMOS Logic for Low Power Design. VLSI Design 2005: 598-605 - [c130]Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell:
Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies. VLSI Design 2005: 723-729 - 2004
- [j120]Vishwani D. Agrawal:
1985 to 1987: My years with D&T. IEEE Des. Test Comput. 21(3): 173-174 (2004) - [j119]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 20(1): 5-6 (2004) - [j118]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 20(2): 127 (2004) - [j117]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 20(3): 219 (2004) - [j116]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 20(4): 327 (2004) - [j115]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 20(5): 459 (2004) - [j114]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 20(6): 571 (2004) - [j113]Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell:
A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults. J. Comput. Sci. Technol. 19(6): 955-964 (2004) - [c129]Junwu Zhang, Michael L. Bushnell, Vishwani D. Agrawal:
On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits. ITC 2004: 617-626 - [c128]Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
A Tuturial on the Emerging Nanotechnology Devices. VLSI Design 2004: 343-360 - [c127]Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. VLSI Design 2004: 1035-1040 - 2003
- [j112]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 19(1): 5 (2003) - [j111]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 19(2): 95 (2003) - [j110]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 19(3): 219 (2003) - [j109]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 19(4): 363 (2003) - [j108]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 19(5): 495 (2003) - [j107]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 19(6): 607 (2003) - [j106]Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul:
A test evaluation technique for VLSI circuits using register-transfer level fault modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(8): 1104-1113 (2003) - [c126]Vishwani D. Agrawal, A. V. S. S. Prasad, Madhusudan V. Atre:
Fault Collapsing via Functional Dominance. ITC 2003: 274-280 - [c125]Vishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja:
Exclusive Test and its Applications to Fault Diagnosis. VLSI Design 2003: 143-148 - [c124]Vishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell:
A Fault-Independent Transitive Closure Algorithm for Redundancy Identification. VLSI Design 2003: 149-154 - [c123]Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal:
New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. VLSI Design 2003: 353-360 - [c122]Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell:
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. VLSI Design 2003: 527-532 - 2002
- [j105]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 18(1): 5 (2002) - [j104]Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal:
State and Fault Information for Compaction-Based Test Generation. J. Electron. Test. 18(1): 63-72 (2002) - [j103]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 18(2): 103-104 (2002) - [j102]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 18(3): 255 (2002) - [j101]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 18(4-5): 359 (2002) - [j100]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 18(6): 567-568 (2002) - [c121]Vivek Gaur, Vishwani D. Agrawal, Michael L. Bushnell:
A New Transitive Closure Algorithm with Application to Redundancy Identification. DELTA 2002: 496-500 - [c120]Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal:
Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. ITC 2002: 375-383 - [c119]A. V. S. S. Prasad, Vishwani D. Agrawal, Madhusudan V. Atre:
A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets. ITC 2002: 391-397 - [c118]Vishwani D. Agrawal, Michael L. Bushnell:
Electronic Testing for SOC Designers (Tutorial Abstract). ASP-DAC/VLSI Design 2002: 20 - [c117]Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja:
Multiple Faults: Modeling, Simulation and Test. ASP-DAC/VLSI Design 2002: 592-597 - 2001
- [j99]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 17(2): 79 (2001) - [j98]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 17(3-4): 203 (2001) - [j97]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 17(5): 367 (2001) - [j96]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 17(6): 455 (2001) - [c116]Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal:
Efficient spectral techniques for sequential ATPG. DATE 2001: 204-208 - [c115]Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja:
Combinational test generation for various classes of acyclic sequential circuits. ITC 2001: 1078-1087 - [c114]Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal:
Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model. VLSI Design 2001: 143-148 - [c113]Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal:
Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment. VTS 2001: 163-168 - 2000
- [j95]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 16(1-2): 5 (2000) - [j94]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 16(3): 163 (2000) - [j93]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 16(4): 315 (2000) - [j92]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 16(5): 403-404 (2000) - [j91]Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi:
False-Path Removal Using Delay Fault Simulation. J. Electron. Test. 16(5): 463-476 (2000) - [j90]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 16(6): 571 (2000) - [j89]Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell:
Path delay fault simulation of sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. 8(2): 223-228 (2000) - [j88]Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell:
Improving path delay testability of sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. 8(6): 736-741 (2000) - [c112]Huan-Chih Tsai, Kwang-Ting Cheng, Vishwani D. Agrawal:
A testability metric for path delay faults and its application. ASP-DAC 2000: 593-598 - [c111]Vishwani D. Agrawal, Kwang-Ting Cheng:
Testing in the Fourth Dimension. Asian Test Symposium 2000: 2 - [c110]Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu:
Collaboration between Industry and Academia in Test Research. Asian Test Symposium 2000: 17 - [c109]Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal:
Compaction-based test generation using state and fault information. Asian Test Symposium 2000: 159-164 - [c108]José T. de Sousa, Vishwani D. Agrawal:
Reducing the Complexity of Defect Level Modeling Using the Clustering Effect. DATE 2000: 640-644 - [c107]Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul:
Register-transfer level fault modeling and test evaluation techniques for VLSI circuits. ITC 2000: 940-949 - [c106]Vishwani D. Agrawal:
Choice of Tests for Logic Verification and Equivalence Checking. VLSI Design 2000: 306-311
1990 – 1999
- 1999
- [j87]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 14(1-2): 7 (1999) - [j86]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 14(3): 187-188 (1999) - [j85]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 15(1-2): 5 (1999) - [j84]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 15(3): 215 (1999) - [c105]Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal:
A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability. Great Lakes Symposium on VLSI 1999: 300- - [c104]Vishwani D. Agrawal:
Panel: Increasing test coverage in a VLSI desgin course. ITC 1999: 1131 - [c103]Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss:
Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. VLSI Design 1999: 434-439 - [c102]Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal:
A Test Generator for Segment Delay Faults. VLSI Design 1999: 484-491 - [c101]Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell:
A Complete Characterization of Path Delay Faults through Stuck-at Faults. VLSI Design 1999: 492-497 - [c100]Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul:
Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test. VTS 1999: 182-188 - 1998
- [j83]Vishwani D. Agrawal:
Editorial. Des. Autom. Embed. Syst. 3(2-3): 115-116 (1998) - [j82]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 12(1-2): 5 (1998) - [j81]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 12(3): 167 (1998) - [j80]Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas:
Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits. J. Electron. Test. 12(3): 239-254 (1998) - [j79]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 13(1): 5 (1998) - [j78]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 13(2): 75 (1998) - [j77]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 13(3): 219 (1998) - [j76]Vishwani D. Agrawal:
Design of mixed-signal systems for testability. Integr. 26(1-2): 141-150 (1998) - [j75]Vishwani D. Agrawal, David Lee, Henryk Wozniakowski:
Numerical computation of characteristic polynomials of Boolean functions and its applications. Numer. Algorithms 17(3-4): 261-278 (1998) - [j74]Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal:
Deriving Logic Systems for Path Delay Test Generation. IEEE Trans. Computers 47(8): 829-846 (1998) - [j73]Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal:
The path-status graph with application to delay fault simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(4): 324-332 (1998) - [j72]Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal:
A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(9): 873-876 (1998) - [j71]Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal:
A rated-clock test method for path delay faults. IEEE Trans. Very Large Scale Integr. Syst. 6(2): 323-331 (1998) - [c99]Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell:
False-Path Removal Using Delay Fault Simulation. Asian Test Symposium 1998: 82-87 - [c98]Vishwani D. Agrawal, Sharad C. Seth:
Mutually Disjoint Signals and Probability Calculation in Digital Circuits. Great Lakes Symposium on VLSI 1998: 307-312 - [c97]Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu:
A non-enumerative path delay fault simulator for sequential circuits. ITC 1998: 934-943 - [c96]Pramit Chavda, James Jacob, Vishwani D. Agrawal:
Optimizing Logic Design Using Boolean Transforms. VLSI Design 1998: 218-221 - [c95]Ananta K. Majhi, Vishwani D. Agrawal:
Mixed-Signal Test. VLSI Design 1998: 285-288 - [c94]Ananta K. Majhi, Vishwani D. Agrawal:
Tutorial: Delay Fault Models and Coverage. VLSI Design 1998: 364-369 - [c93]Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal:
Path Delay Testing: Variable-Clock Versus Rated-Clock. VLSI Design 1998: 470-475 - [c92]Subhashis Majumder, Vishwani D. Agrawal, Michael L. Bushnell:
On Delay-Untestable Paths and Stuck-Fault Redundancy. VTS 1998: 194-199 - 1997
- [j70]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 10(1-2): 5 (1997) - [j69]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 10(3): 171 (1997) - [j68]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 11(1): 5 (1997) - [j67]Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal:
Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests. J. Electron. Test. 11(1): 55-67 (1997) - [j66]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 11(2): 107 (1997) - [j65]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 11(3): 195 (1997) - [j64]Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel:
Improving a nonenumerative method to estimate path delay fault coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(7): 759-762 (1997) - [j63]Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell:
On variable clock methods for path delay testing of sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11): 1237-1249 (1997) - [j62]Srimat T. Chakradhar, Steven G. Rothweiler, Vishwani D. Agrawal:
Redundancy removal and test generation for circuits with non-Boolean primitives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11): 1370-1377 (1997) - [j61]Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal:
Scheduling tests for VLSI systems under power constraints. IEEE Trans. Very Large Scale Integr. Syst. 5(2): 175-185 (1997) - [c91]Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal:
Fast identification of untestable delay faults using implications. ICCAD 1997: 642-647 - [c90]Soumitra Bose, Vishwani D. Agrawal, Thomas G. Szymanski:
Algorithms for Switch Level Delay Fault Simulation. ITC 1997: 982-991 - [c89]Tapan J. Chakraborty, Vishwani D. Agrawal:
Effective Path Selection for Delay Fault Testing of Sequential Circuits. ITC 1997: 998-1003 - [c88]Mandyam-Komar Srinivas, Michael L. Bushnell, Vishwani D. Agrawal:
Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation. VLSI Design 1997: 88-94 - [c87]Vishwani D. Agrawal:
Low-Power Design by Hazard Filtering. VLSI Design 1997: 193-197 - [c86]James Jacob, P. Srinivas Sivakumar, Vishwani D. Agrawal:
Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs. VLSI Design 1997: 514-515 - [c85]Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian:
Power Dissipation During Testing: Should We Worry About it? VTS 1997: 456-457 - 1996
- [j60]Vishwani D. Agrawal:
1995 Asian Test Symposium carves a niche. IEEE Des. Test Comput. 13(2): 3- (1996) - [j59]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 8(2): 111 (1996) - [j58]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 9(1-2): 5 (1996) - [j57]Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal:
Functional test generation for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(7): 831-843 (1996) - [c84]Vishwani D. Agrawal, Michael L. Bushnell, Qing Lin:
Redundancy Identification Using Transitive Closure. Asian Test Symposium 1996: 4-9 - [c83]Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal:
Improving Circuit Testability by Clock Control. Great Lakes Symposium on VLSI 1996: 288-293 - [c82]Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal:
SIGMA: a simulator for segment delay faults. ICCAD 1996: 502-508 - [c81]Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal:
An Exact Non-Enumerative Fault Simulator for Path-Delay Faults. ITC 1996: 276-285 - [c80]Vishwani D. Agrawal, Ronald D. Blanton, Maurizio Damiani:
Synthesis of Self-Testing Finite State Machines from High-Level Specifications. ITC 1996: 757-766 - [c79]Vishwani D. Agrawal:
Science, Technology, and the Indian Society. VLSI Design 1996: 6-9 - [c78]Tapan J. Chakraborty, Vishwani D. Agrawal:
Design for high-speed testability of stuck-at faults. VLSI Design 1996: 53-56 - [c77]Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas:
Statistical path delay fault coverage estimation for synchronous sequential circuits. VLSI Design 1996: 290-295 - [c76]Vishwani D. Agrawal, David Lee:
Characteristic polynomial method for verification and test of combinational circuits. VLSI Design 1996: 341-342 - [c75]Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal:
On test coverage of path delay faults. VLSI Design 1996: 418-421 - [c74]Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal:
Improving accuracy in path delay fault coverage estimation. VLSI Design 1996: 422-425 - [c73]Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal:
Parallel concurrent path-delay fault simulation using single-input change patterns. VLSI Design 1996: 426-431 - [c72]Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal:
Segment delay faults: a new fault model. VTS 1996: 32-41 - 1995
- [j56]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 6(1): 5-6 (1995) - [j55]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 6(2): 147 (1995) - [j54]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 6(3): 263 (1995) - [j53]Vishwani D. Agrawal:
Editorial - Special issue on partial scan design. J. Electron. Test. 7(1-2): 5-6 (1995) - [j52]Srimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal:
An exact algorithm for selecting partial scan flip-flops. J. Electron. Test. 7(1-2): 83-93 (1995) - [j51]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 7(3): 143 (1995) - [j50]Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal:
Test Generation for Path Delay Faults Using Binary Decision Diagrams. IEEE Trans. Computers 44(3): 434-447 (1995) - [j49]Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell:
Fault coverage estimation by test vector sampling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5): 590-596 (1995) - [j48]Srimat T. Chakradhar, Mahesh A. Iyer, Vishwani D. Agrawal:
Energy models for delay testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(6): 728-739 (1995) - [j47]Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal:
Test function embedding algorithms with application to interconnected finite state machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1115-1127 (1995) - [j46]Vishwani D. Agrawal, Srimat T. Chakradhar:
Combinational ATPG theorems for identifying untestable faults in sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1155-1160 (1995) - [j45]Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal:
A partition and resynthesis approach to testable design of large circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(10): 1268-1276 (1995) - [c71]Vishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, Sandip Kundu, Chung-Len Lee, Yinghua Min, Parimal Pal Chaudhuri:
Panel: New Research Problems in the Emerging Test Technology. Asian Test Symposium 1995: 189-190 - [c70]Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell:
Functional test generation for path delay faults. Asian Test Symposium 1995: 339-345 - [c69]Soumitra Bose, Vishwani D. Agrawal:
Sequential logic path delay test generation by symbolic analysis. Asian Test Symposium 1995: 353- - [c68]James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal:
An adaptive distributed algorithm for sequential circuit test generation. EURO-DAC 1995: 236-241 - [c67]Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal:
Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests. ITC 1995: 139-148 - [c66]Vishwani D. Agrawal, Tapan J. Chakraborty:
High-Performance Circuit Testing with Slow-Speed Testers. ITC 1995: 302-310 - [c65]James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal:
An asynchronous algorithm for sequential circuit test generation on a network of workstations. VLSI Design 1995: 36-41 - [c64]Tapan J. Chakraborty, Vishwani D. Agrawal:
Robust testing for stuck-at faults. VLSI Design 1995: 42-46 - [c63]Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal:
Functional test generation for non-scan sequential circuits. VLSI Design 1995: 47-52 - [c62]Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal:
An efficient automatic test generation system for path delay faults in combinational circuits. VLSI Design 1995: 161-165 - [c61]Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell:
Statistical methods for delay fault coverage analysis. VLSI Design 1995: 166-170 - [c60]Tapan J. Chakraborty, Vishwani D. Agrawal:
Simulation of at-speed tests for stuck-at faults. VTS 1995: 216-220 - 1994
- [b1]Ernst G. Ulrich, Vishwani D. Agrawal, Jack H. Arabian:
Concurrent and comparative discrete event simulation. Kluwer 1994, ISBN 978-0-7923-9411-2, pp. I-XIII, 1-186 - [j44]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 5(1): 5 (1994) - [j43]Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell:
Energy minimization and design for testability. J. Electron. Test. 5(1): 57-66 (1994) - [j42]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 5(2-3): 127 (1994) - [j41]Vishwani D. Agrawal:
A tale of two designs: the cheapest and the most economic. J. Electron. Test. 5(2-3): 131-135 (1994) - [j40]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 5(4): 317 (1994) - [c59]Srimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal:
An Exact Algorithm for Selecting Partial Scan Flip-Flops. DAC 1994: 81-86 - [c58]Keerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal:
An Efficient Path Delay Fault Coverage Estimator. DAC 1994: 516-521 - [c57]Tapan J. Chakraborty, Vishwani D. Agrawal:
Delay independent initialization of sequential circuits. Great Lakes Symposium on VLSI 1994: 228-230 - [c56]Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal:
A Test Function Architecture for Interconnected Finite State Machines. VLSI Design 1994: 113-116 - [c55]Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal:
Power Constraint Scheduling of Tests. VLSI Design 1994: 271-274 - [c54]P. R. Suresh Kumar, James Jacob, Mandyam-Komar Srinivas, Vishwani D. Agrawal:
An Improved Deductive Fault Simulator. VLSI Design 1994: 307-310 - [c53]Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell:
FACTS: fault coverage estimation by test vector sampling. VTS 1994: 266-271 - 1993
- [j39]Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth:
Generating Tests for Delay Faults in Nonscan Circuits. IEEE Des. Test Comput. 10(1): 20-28 (1993) - [j38]Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja:
A Tutorial on Built-in Self-Test. I. Principles. IEEE Des. Test Comput. 10(1): 73-82 (1993) - [j37]Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja:
A Tutorial on Built-In Self-Test, Part 2: Applications. IEEE Des. Test Comput. 10(2): 69-77 (1993) - [j36]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 4(1): 5 (1993) - [j35]Srimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal:
Finite state machine synthesis with fault tolerant test function. J. Electron. Test. 4(1): 57-69 (1993) - [j34]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 4(2): 123 (1993) - [j33]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 4(3): 199 (1993) - [j32]Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal:
The optimistic update theorem for path delay testing in sequential circuits. J. Electron. Test. 4(3): 285-290 (1993) - [j31]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 4(4): 295 (1993) - [j30]Srimat T. Chakradhar, Vishwani D. Agrawal, Steven G. Rothweiler:
A transitive closure algorithm for test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(7): 1015-1028 (1993) - [j29]Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal:
Path delay fault simulation of sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. 1(4): 453-461 (1993) - [j28]D. Das, Sharad C. Seth, Vishwani D. Agrawal:
Accurate computation of field reject ratio based on fault latency. IEEE Trans. Very Large Scale Integr. Syst. 1(4): 537-545 (1993) - [c52]Prathima Agrawal, Vishwani D. Agrawal, Joan Villoldo:
Sequential Circuit Test Generation on a Distributed System. DAC 1993: 107-111 - [c51]Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell:
Design for Testability for Path Delay faults in Sequential Circuits. DAC 1993: 453-457 - [c50]Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal:
Logic systems for path delay test generation. EURO-DAC 1993: 200-205 - [c49]Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal:
Test function embedding algorithms with application to interconnected finite state machines. EURO-DAC 1993: 219-224 - [c48]Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal:
Delay fault testability evaluation through timing simulation. Great Lakes Symposium on VLSI 1993: 18-21 - [c47]Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal:
Clock partitioning for testability. Great Lakes Symposium on VLSI 1993: 42-46 - [c46]Prathima Agrawal, Vishwani D. Agrawal, Joan Villoldo:
Test Pattern Generation for Sequential Circuits on a Network of Workstations. HPDC 1993: 114-120 - [c45]Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal:
Generation of Compact Delay Tests by Multiple-Path Activation. ITC 1993: 714-723 - [c44]Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal:
A Synthesis Approach to Design for Testability. ITC 1993: 754-763 - [c43]Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal:
A Path Delay Fault Simulator for Sequential Circuits. VLSI Design 1993: 269-274 - [c42]Vishwani D. Agrawal, Tapan J. Chakraborty:
Partial scan testing with single clock control. VTS 1993: 313-315 - 1992
- [j27]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 3(2): 105 (1992) - [j26]Ernst G. Ulrich, Karen Lentz, Jack H. Arabian, Michael Gustin, Vishwani D. Agrawal, Pier Luca Montessoro:
The Comparative and Concurrent Simulation of discrete-event experiments. J. Electron. Test. 3(2): 107-118 (1992) - [j25]James Jacob, Vishwani D. Agrawal:
Multiple fault detection in two-level multi-output circuits. J. Electron. Test. 3(2): 171-173 (1992) - [j24]Kwang-Ting Cheng, Vishwani D. Agrawal:
Initializability Consideration in Sequential Machine Synthesis. IEEE Trans. Computers 41(3): 374-379 (1992) - [j23]Vishwani D. Agrawal, Srimat T. Chakradhar:
Performance Analysis of Synchronized Iterative Algorithms on Multiprocessor Systems. IEEE Trans. Parallel Distributed Syst. 3(6): 739-746 (1992) - [c41]Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal:
Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions. DAC 1992: 159-164 - [c40]Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell:
Delay Fault Models and Test Generation for Random Logic Sequential Circuits. DAC 1992: 165-172 - [c39]Srimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal:
Finite State Machine Synthesis with Fault Tolerant Test Function. DAC 1992: 562-567 - [c38]Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth:
DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits. EURO-DAC 1992: 138-141 - [c37]Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal:
Finite State Machine Testing Based on Growth and Dissappearance Faults. FTCS 1992: 238-245 - [c36]Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth:
A New Method for Generating Tests for Delay Faults in Non-Scan Circuits. VLSI Design 1992: 4-11 - [c35]James Jacob, Vishwani D. Agrawal:
Functional Test Generation for Sequential Circuits. VLSI Design 1992: 17-24 - 1991
- [c34]Srimat T. Chakradhar, Vishwani D. Agrawal:
A Transitive Closure Based Algorithm for Test Generation. DAC 1991: 353-358 - [c33]Vishwani D. Agrawal:
Design and Test-The Two Sides of a Coin. ICCD 1991: 12 - [c32]Joan Villoldo, Prathima Agrawal, Vishwani D. Agrawal:
Stafan Algorithms for MOS Circuits. ICCD 1991: 56-59 - [c31]Dharam Vir Das, Sharad C. Seth, Vishwani D. Agrawal:
Estimating the Quality of Manufactured Digital Sequential Circuits. ITC 1991: 210-217 - 1990
- [j22]Vishwani D. Agrawal, Hatsuyoshi Kato:
Fault Sampling Revisited. IEEE Des. Test Comput. 7(4): 32-35 (1990) - [j21]Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell, Thomas K. Truong:
Neural Net and Boolean Satisfiability Models of Logic Circuits. IEEE Des. Test Comput. 7(5): 54-57 (1990) - [j20]Vishwani D. Agrawal:
Editorial. J. Electron. Test. 1(2): 101 (1990) - [j19]Vishwani D. Agrawal, Kwang-Ting Cheng:
Finite state machine synthesis with embedded test function. J. Electron. Test. 1(3): 221-228 (1990) - [j18]Kwang-Ting Cheng, Vishwani D. Agrawal:
A Partial Scan Method for Sequential Circuits with Feedback. IEEE Trans. Computers 39(4): 544-549 (1990) - [j17]Sharad C. Seth, Vishwani D. Agrawal, Hassan Farhat:
A Statistical Theory of Digital Circuit Testability. IEEE Trans. Computers 39(4): 582-586 (1990) - [j16]Kwang-Ting Cheng, Vishwani D. Agrawal, Ernest S. Kuh:
A Simulation-Based Method for Generating Tests for Sequential Circuits. IEEE Trans. Computers 39(12): 1456-1463 (1990) - [j15]Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal:
Toward massively parallel automatic test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(9): 981-994 (1990) - [c30]Vishwani D. Agrawal, Kwang-Ting Cheng:
Test Function Specification in Synthesis. DAC 1990: 235-240 - [c29]Kwang-Ting Cheng, Vishwani D. Agrawal:
An Entropy Measure for the Complexity of Multi-Output Boolean Functions. DAC 1990: 302-305 - [c28]Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell:
Automatic Test Generation Using Quadratic 0-1 Programming. DAC 1990: 654-659 - [c27]Vishwani D. Agrawal, Kwang-Ting Cheng:
An architecture for synthesis of testable finite state machines. EURO-DAC 1990: 612-616 - [c26]Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell:
Polynomial time solvable fault detection problems. FTCS 1990: 56-63 - [c25]Vishwani D. Agrawal, Srimat T. Chakradhar:
Logic Simulation and Parallel Processing. ICCAD 1990: 496-499 - [c24]Dharam Vir Das, Sharad C. Seth, Paul T. Wagner, John C. Anderson, Vishwani D. Agrawal:
An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisited. ITC 1990: 712-720 - [c23]Vishwani D. Agrawal, Srimat T. Chakradhar:
Performance estimation in a massively parallel system. SC 1990: 306-313
1980 – 1989
- 1989
- [j14]Sharad C. Seth, Vishwani D. Agrawal:
A new model for computation of probabilistic testability in combinational circuits. Integr. 7(1): 49-75 (1989) - [j13]Sharad C. Seth, Vishwani D. Agrawal:
A new model for computation of probabilistic testability in combinational circuits. Integr. 7(3): 325 (1989) - [j12]Vishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal:
A directed search method for test generation using a concurrent simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(2): 131-138 (1989) - [c22]Kwang-Ting Cheng, Vishwani D. Agrawal:
An economical scan design for sequential logic test generation. FTCS 1989: 28-35 - [c21]Kwang-Ting Cheng, Vishwani D. Agrawal:
State assignment for initializable synthesis (gate level analysis). ICCAD 1989: 212-215 - [c20]Kwang-Ting Cheng, Vishwani D. Agrawal:
Design of sequential machines for efficient test generation. ICCAD 1989: 358-361 - [c19]Prathima Agrawal, Vishwani D. Agrawal, Kwang-Ting Cheng, Raffi Tutundjian:
Fault Simulation in a Pipelined Multiprocessor System. ITC 1989: 727-734 - 1988
- [j11]Vishwani D. Agrawal, Kwang-Ting Cheng, Daniel D. Johnson, Tonysheng Lin:
Designing circuits with partial scan. IEEE Des. Test 5(2): 8-15 (1988) - [c18]Vishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal:
Contest: A Concurrent Test Generator for Sequential Circuits. DAC 1988: 84-89 - [c17]Kwang-Ting Cheng, Vishwani D. Agrawal, Ernest S. Kuh:
A sequential circuit test generation using threshold-value simulation. FTCS 1988: 24-29 - [c16]Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal:
Automatic test generation using neural networks. ICCAD 1988: 416-419 - [c15]Vishwani D. Agrawal, Hassan Farhat, Sharad Seth:
Test generation by fault sampling. ICCD 1988: 58-61 - 1986
- [c14]Vishwani D. Agrawal, M. Ray Mercer:
Deterministic Versus Random Testing. ITC 1986: 718 - 1985
- [j10]Sunil K. Jain, Vishwani D. Agrawal:
Statistical Fault Analysis. IEEE Des. Test 2(1): 38-44 (1985) - [j9]Sunil K. Jain, Vishwani D. Agrawal:
Modeling and Test Generation Algorithms for MOS Circuits. IEEE Trans. Computers 34(5): 426-433 (1985) - [c13]Vishwani D. Agrawal, Samuel H. C. Poon:
VLSI design process. ACM Conference on Computer Science 1985: 74-78 - [c12]Prathima Agrawal, Vishwani D. Agrawal, Nripendra N. Biswas:
Multiple output minimization. DAC 1985: 674-680 - [c11]Vishwani D. Agrawal:
STAFAN Takes a Middle Course. ITC 1985: 796 - 1984
- [j8]Sharad C. Seth, Vishwani D. Agrawal:
Characterizing the LSI Yield Equation from Wafer Test Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3(2): 123-126 (1984) - [c10]Sunil K. Jain, Vishwani D. Agrawal:
STAFAN: An alternative to fault simulation. DAC 1984: 18-23 - [c9]Alfred E. Dunlop, Vishwani D. Agrawal, David N. Deutsch, M. F. Jukl, Patrick Kozak, Manfred Wiesel:
Chip layout optimization using critical path weighting. DAC 1984: 133-136 - [c8]Sudhakar M. Reddy, Vishwani D. Agrawal, Sunil K. Jain:
A gate level model for CMOS combinational logic circuits with application to fault detection. DAC 1984: 504-509 - [c7]Vishwani D. Agrawal:
Will Testability Analysis Replace Fault Simulation ? ITC 1984: 718-718 - 1983
- [c6]Sunil K. Jain, Vishwani D. Agrawal:
Test generation for MOS circuits using D-algorithm. DAC 1983: 64-70 - 1982
- [c5]Vishwani D. Agrawal:
Synchronous path analysis in MOS circuit simulator. DAC 1982: 629-635 - [c4]Vishwani D. Agrawal, M. Ray Mercer:
Testability Measures : What Do They Tell Us ? ITC 1982: 391-399 - 1981
- [j7]Vishwani D. Agrawal:
An Information Theoretic Approach to Digital Fault Testing. IEEE Trans. Computers 30(8): 582-587 (1981) - [c3]Vishwani D. Agrawal, Sharad C. Seth, Prathima Agrawal:
LSI product quality and fault coverage. DAC 1981: 196-203 - [c2]M. Ray Mercer, Vishwani D. Agrawal, Carlos M. Roman:
Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation. ITC 1981: 561-565 - 1980
- [c1]Vishwani D. Agrawal, Ajoy K. Bose, Patrick Kozak, Hao N. Nham, Ernesto Pacas-Skewes:
A mixed-mode simulator. DAC 1980: 618-625
1970 – 1979
- 1979
- [j6]Vishwani D. Agrawal:
Author's Reply. IEEE Trans. Computers 28(8): 581 (1979) - [j5]Vishwani D. Agrawal:
Comments on "An Approach to Highly Integrated Computer-Maintained Cellular Arrays". IEEE Trans. Computers 28(9): 691-693 (1979) - 1978
- [j4]Vishwani D. Agrawal:
When to Use Random Testing. IEEE Trans. Computers 27(11): 1054-1055 (1978) - 1976
- [j3]Prathima Agrawal, Vishwani D. Agrawal:
On Monte Carlo Testing of Logic Tree Networks. IEEE Trans. Computers 25(6): 664-667 (1976) - 1975
- [j2]Prathima Agrawal, Vishwani D. Agrawal:
Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks. IEEE Trans. Computers 24(7): 691-695 (1975) - 1972
- [j1]Vishwani D. Agrawal, Prathima Agrawal:
An Automatic Test Generation System for Illiac IV Logic Boards. IEEE Trans. Computers 21(9): 1015-1017 (1972)
Coauthor Index
[j141] [c150] [j132] [c147] [j128] [c132] [c131] [c130] [j113] [c129] [c128] [c127] [c124] [c123] [c122] [c121] [c120] [c118] [j91] [j89] [j88] [c103] [c101] [j80] [j73] [j72] [c99] [c97] [c93] [c92] [j67] [j64] [j63] [c88] [c84] [c81] [c77] [c73] [j49] [c70] [c68] [c67] [c65] [c61] [j43] [c58] [c53] [c51] [c40] [j21] [j15] [c28] [c26] [c16]
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