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Sung Kyu Lim
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- affiliation: Georgia Institute of Technology, Atlanta GA, USA
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2020 – today
- 2024
- [j109]Sai Pentapati
, Kyungwook Chang
, Sung Kyu Lim
:
Pin-3D: Effective Physical Design Methodology for Multidie Co-Optimization in Monolithic 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1009-1022 (2024) - [j108]Nesara Eranna Bethur
, Anthony Agnesina
, Moritz Brunion
, Alberto García Ortiz
, Francky Catthoor
, Dragomir Milojevic, Manu Komalan
, Matheus A. Cavalcante, Samuel Riedel
, Luca Benini
, Sung Kyu Lim
:
Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(7): 1957-1970 (2024) - [j107]Yen-Hsiang Huang, Sai Pentapati, Anthony Agnesina, Moritz Brunion, Sung Kyu Lim:
On Legalization of Die Bonding Bumps and Pads for 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(9): 2741-2754 (2024) - [j106]Yi-Chen Lu
, Haoxing Ren
, Hao-Hsiang Hsiao
, Sung Kyu Lim
:
GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning. ACM Trans. Design Autom. Electr. Syst. 29(2): 32:1-32:17 (2024) - [j105]Jinwoo Kim
, Lingjun Zhu
, Hakki Mert Torun
, Madhavan Swaminathan
, Sung Kyu Lim
:
A PPA Study for Heterogeneous 3-D IC Options: Monolithic, Hybrid Bonding, and Microbumping. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 401-412 (2024) - [j104]Sai Pentapati
, Sung Kyu Lim
:
Heterogeneous Monolithic 3-D IC Designs: Challenges, EDA Solutions, and Power, Performance, Cost Tradeoffs. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 413-421 (2024) - [c201]Hao-Hsiang Hsiao
, Yi-Chen Lu
, Pruek Vanna-Iampikul
, Sung Kyu Lim
:
FastTuner: Transferable Physical Design Parameter Optimization using Fast Reinforcement Learning. ISPD 2024: 93-101 - 2023
- [j103]Jeffrey S. Vetter
, Prasanna Date, Farah Fahim, Shruti R. Kulkarni, Petro Maksymovych, A. Alec Talin, Marc González Tallada, Pruek Vanna-Iampikul
, Aaron R. Young
, David Brooks, Yu Cao, Gu-Yeon Wei, Sung Kyu Lim, Frank Liu, Matthew J. Marinella, Bobby G. Sumpter, Narasinga Rao Miniskar:
Abisko: Deep codesign of an architecture for spiking neural networks using novel neuromorphic materials. Int. J. High Perform. Comput. Appl. 37(3-4): 351-379 (2023) - [j102]Anthony Agnesina
, Kyungwook Chang
, Sung Kyu Lim:
Parameter Optimization of VLSI Placement Through Deep Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1295-1308 (2023) - [j101]Pruek Vanna-Iampikul
, Chengjia Shao
, Yi-Chen Lu
, Sai Pentapati
, Yun Heo, Jae-Seung Choi, Sung Kyu Lim:
Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2331-2335 (2023) - [j100]Shao-Chun Hung
, Sanmitra Banerjee, Arjun Chaudhuri
, Jinwoo Kim
, Sung Kyu Lim, Krishnendu Chakrabarty
:
Transferable Graph Neural Network-Based Delay-Fault Localization for Monolithic 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4296-4309 (2023) - [j99]Yi-Chen Lu
, Siddhartha Nath
, Sai Pentapati
, Sung Kyu Lim
:
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation. ACM Trans. Design Autom. Electr. Syst. 28(4): 55:1-55:22 (2023) - [j98]Gauthaman Murali
, Anthony Agnesina
, Sung Kyu Lim
:
A PPA Study of Reinforced Placement Parameter Autotuning: Pseudo-3D vs. True-3D Placers. ACM Trans. Design Autom. Electr. Syst. 28(5): 75:1-75:22 (2023) - [j97]Pruek Vanna-Iampikul
, Yi-Chen Lu
, Da Eun Shim
, Sung Kyu Lim
:
GNN-based Multi-bit Flip-flop Clustering and Post-clustering Design Optimization for Energy-efficient 3D ICs. ACM Trans. Design Autom. Electr. Syst. 28(5): 76:1-76:26 (2023) - [j96]Arjun Chaudhuri
, Sanmitra Banerjee, Jinwoo Kim
, Sung Kyu Lim, Krishnendu Chakrabarty
:
Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 31(3): 296-309 (2023) - [j95]Gauthaman Murali
, Aditya Iyer
, Lingjun Zhu
, Jianming Tong
, Francisco Muñoz-Martínez
, Srivatsa Rangachar Srinivasa, Tanay Karnik
, Tushar Krishna
, Sung Kyu Lim:
On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 31(10): 1603-1613 (2023) - [c200]Yi-Chen Lu, Wei-Ting Chan, Deyuan Guo, Sudipto Kundu, Vishal Khandelwal, Sung Kyu Lim:
RL-CCD: Concurrent Clock and Data Optimization using Attention-Based Self-Supervised Reinforcement Learning. DAC 2023: 1-6 - [c199]Pruek Vanna-Iampikul, Lingjun Zhu, Serhat Erdogan, Mohanalingam Kathaperumal, Ravi Agarwal, Ram Gupta, Kevin Rinebold, Sung Kyu Lim:
Glass Interposer Integration of Logic and Memory Chiplets: PPA and Power/Signal Integrity Benefits. DAC 2023: 1-6 - [c198]Lingjun Zhu, Sung Kyu Lim:
INVITED: Design Automation Needs for Monolithic 3D ICs: Accomplishments and Gaps. DAC 2023: 1-4 - [c197]Tathagata Srimani, Robert M. Radway, Jinwoo Kim, Kartik Prabhu, Dennis Rich
, Carlo Gilardi, Priyanka Raina, Max M. Shulaker, Sung Kyu Lim, Subhasish Mitra:
Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits. DATE 2023: 1-6 - [c196]Jonti Talukdar, Arjun Chaudhuri, Jinwoo Kim, Sung Kyu Lim, Krishnendu Chakrabarty:
Securing Heterogeneous 2.5D ICs Against IP Theft through Dynamic Interposer Obfuscation. DATE 2023: 1-2 - [c195]Gauthaman Murali, Aditya Iyer, Navneeth Ravichandran, Sung Kyu Lim:
3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3D DNN Accelerators. ICCAD 2023: 1-9 - [c194]Narasinga Rao Miniskar, Pruek Vanna-Iampikul
, Aaron R. Young
, Sung Kyu Lim, Frank Liu, Jieun Yoo, Corrinne Mills, Nhan Tran, Farah Fahim, Jeffrey S. Vetter:
A 3D Implementation of Convolutional Neural Network for Fast Inference. ISCAS 2023: 1-5 - [c193]Sandra Maria Shaji, Lingjun Zhu, Jun-Sik Yoon, Sung Kyu Lim:
A Comparative Study on Front-Side, Buried and Back-Side Power Rail Topologies in 3nm Technology Node. ISLPED 2023: 1-6 - [c192]Sai Pentapati
, Anthony Agnesina
, Moritz Brunion
, Yen-Hsiang Huang
, Sung Kyu Lim
:
On Legalization of Die Bonding Bumps and Pads for 3D ICs. ISPD 2023: 62-70 - [c191]Yi-Chen Lu
, Haoxing Ren
, Hao-Hsiang Hsiao
, Sung Kyu Lim
:
DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality using Generative Adversarial Learning. ISPD 2023: 141-148 - 2022
- [j94]Yandong Luo
, Sourav Dutta
, Ankit Kaul
, Sung Kyu Lim, Muhannad S. Bakir, Suman Datta
, Shimeng Yu
:
A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 445-457 (2022) - [j93]Edward Lee, Daehyun Kim, Jinwoo Kim, Sung Kyu Lim, Saibal Mukhopadhyay:
A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube Process. ACM J. Emerg. Technol. Comput. Syst. 18(1): 20:1-20:20 (2022) - [j92]Lingjun Zhu, Arjun Chaudhuri, Sanmitra Banerjee, Gauthaman Murali
, Pruek Vanna-Iampikul
, Krishnendu Chakrabarty, Sung Kyu Lim:
Design Automation and Test Solutions for Monolithic 3D ICs. ACM J. Emerg. Technol. Comput. Syst. 18(1): 21:1-21:49 (2022) - [j91]Arjun Chaudhuri, Sanmitra Banerjee, Jinwoo Kim, Heechun Park, Bon Woong Ku, Sukeshwar Kannan, Krishnendu Chakrabarty, Sung Kyu Lim:
Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs. ACM J. Emerg. Technol. Comput. Syst. 18(1): 22:1-22:37 (2022) - [j90]Bon Woong Ku, Catherine D. Schuman
, Md Musabbir Adnan, Tiffany M. Mintz, Raphael C. Pooser, Kathleen E. Hamilton, Garrett S. Rose
, Sung Kyu Lim:
Unsupervised Digit Recognition Using Cosine Similarity In A Neuromemristive Competitive Learning System. ACM J. Emerg. Technol. Comput. Syst. 18(2): 38:1-38:20 (2022) - [j89]Kyungwook Chang
, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
:
Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 410-423 (2022) - [j88]Yi-Chen Lu
, Jeehyun Lee
, Anthony Agnesina
, Kambiz Samadi, Sung Kyu Lim:
A Clock Tree Prediction and Optimization Framework Using Generative Adversarial Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 3104-3117 (2022) - [j87]Yi-Chen Lu
, Sai Pentapati
, Lingjun Zhu
, Gauthaman Murali
, Kambiz Samadi, Sung Kyu Lim
:
A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4575-4586 (2022) - [j86]Sai Pentapati
, Sung Kyu Lim:
Metal Layer Sharing: A Routing Optimization Technique for Monolithic 3D ICs. IEEE Trans. Very Large Scale Integr. Syst. 30(9): 1355-1367 (2022) - [c190]Matheus A. Cavalcante
, Anthony Agnesina, Samuel Riedel
, Moritz Brunion, Alberto García-Ortiz, Dragomir Milojevic
, Francky Catthoor, Sung Kyu Lim, Luca Benini:
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration. DATE 2022: 394-399 - [c189]Yi-Chen Lu, Sung Kyu Lim:
On Advancing Physical Design Using Graph Neural Networks. ICCAD 2022: 2:1-2:7 - [c188]Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic
, Manu Komalan, Matheus A. Cavalcante
, Samuel Riedel
, Luca Benini, Sung Kyu Lim:
Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs. ISLPED 2022: 15:1-15:6 - [c187]Lingjun Zhu, Nesara Eranna Bethur, Yi-Chen Lu, Youngsang Cho, Yunhyeok Im, Sung Kyu Lim:
3D IC Tier Partitioning of Memory Macros: PPA vs. Thermal Tradeoffs. ISLPED 2022: 19:1-19:6 - [c186]Gauthaman Murali
, Sandra Maria Shaji, Anthony Agnesina, Guojie Luo, Sung Kyu Lim:
ART-3D: Analytical 3D Placement with Reinforced Parameter Tuning for Monolithic 3D ICs. ISPD 2022: 97-104 - [c185]Sai Pentapati, Sung Kyu Lim:
Routing Layer Sharing: A New Opportunity for Routing Optimization in Monolithic 3D ICs. ISPD 2022: 127-134 - [c184]Yi-Chen Lu, Tian Yang, Sung Kyu Lim, Haoxing Ren:
Placement Optimization via PPA-Directed Graph Clustering. MLCAD 2022: 1-6 - [c183]Yi-Chen Lu, Wei-Ting Chan, Vishal Khandelwal, Sung Kyu Lim:
Driving Early Physical Synthesis Exploration through End-of-Flow Total Power Prediction. MLCAD 2022: 97-102 - 2021
- [j85]Heechun Park, Bon Woong Ku, Kyungwook Chang, Da Eun Shim, Sung Kyu Lim
:
Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements. ACM Trans. Design Autom. Electr. Syst. 26(5): 37:1-37:25 (2021) - [j84]Gauthaman Murali
, Xiaoyu Sun, Shimeng Yu
, Sung Kyu Lim
:
Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM. IEEE Trans. Very Large Scale Integr. Syst. 29(2): 386-396 (2021) - [j83]Gauthaman Murali
, Heechun Park
, Eric Qin, Hakki Mert Torun
, Majid Ahadi Dolatsara
, Madhavan Swaminathan, Tushar Krishna
, Sung Kyu Lim
:
Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 605-616 (2021) - [j82]Lingjun Zhu
, Lennart Bamberg
, Sai Surya Kiran Pentapati
, Kyungwook Chang
, Francky Catthoor, Dragomir Milojevic
, Manu Komalan
, Brian Cline, Saurabh Sinha, Xiaoqing Xu, Alberto García-Ortiz
, Sung Kyu Lim
:
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1152-1163 (2021) - [j81]Shao-Chun Hung
, Yi-Chen Lu
, Sung Kyu Lim, Krishnendu Chakrabarty
:
Power Supply Noise-Aware At-Speed Delay Fault Testing of Monolithic 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 29(11): 1875-1888 (2021) - [c182]Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim
:
RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning. DAC 2021: 733-738 - [c181]Sai Surya Kiran Pentapati, Sung Kyu Lim
:
Heterogeneous Monolithic 3D ICs: EDA Solutions, and Power, Performance, Cost Tradeoffs. DAC 2021: 925-930 - [c180]Jinwoo Kim, Lingjun Zhu, Hakki Mert Torun, Madhavan Swaminathan, Sung Kyu Lim
:
Micro-bumping, Hybrid Bonding, or Monolithic? A PPA Study for Heterogeneous 3D IC Options. DAC 2021: 1189-1194 - [c179]Gauthaman Murali
, Sung Kyu Lim
:
Heterogeneous 3D ICs: Current Status and Future Directions for Physical Design Technologies. DATE 2021: 146-151 - [c178]Bahar Asgari
, Ramyad Hadidi, Jiashen Cao, Da Eun Shim, Sung Kyu Lim
, Hyesoon Kim:
FAFNIR: Accelerating Sparse Gathering by Using Efficient Near-Memory Intelligent Reduction. HPCA 2021: 908-920 - [c177]Sanmitra Banerjee, Arjun Chaudhuri, Jinwoo Kim, Gauthaman Murali
, Mark Nelson, Sung Kyu Lim, Krishnendu Chakrabarty:
ParaMitE: Mitigating Parasitic CNFETs in the Presence of Unetched CNTs. ICCAD 2021: 1-9 - [c176]Johann Knechtel, Jayanth Gopinath, Jitendra Bhandari, Mohammed Ashraf, Hussam Amrouch, Shekhar Borkar, Sung Kyu Lim, Ozgur Sinanoglu, Ramesh Karri
:
Security Closure of Physical Layouts ICCAD Special Session Paper. ICCAD 2021: 1-9 - [c175]Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim:
Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning. ICCAD 2021: 1-9 - [c174]Anthony Agnesina, Moritz Brunion, Jinwoo Kim, Alberto García Ortiz, Dragomir Milojevic
, Francky Catthoor, Manu Perumkunnil, Sung Kyu Lim
:
Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs. ISLPED 2021: 1-6 - [c173]Lingjun Zhu, Tuan Ta, Rossana Liu, Rahul Mathur
, Xiaoqing Xu, Shidhartha Das, Ankit Kaul, Alejandro Rico, Doug Joseph, Brian Cline, Sung Kyu Lim
:
Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture. ISLPED 2021: 1-6 - [c172]Yi-Chen Lu, Sai Pentapati, Sung Kyu Lim
:
The Law of Attraction: Affinity-Aware Placement Optimization using Graph Neural Networks. ISPD 2021: 7-14 - [c171]Pruek Vanna-Iampikul
, Chengjia Shao, Yi-Chen Lu, Sai Pentapati, Sung Kyu Lim
:
Snap-3D: A Constrained Placement-Driven Physical Design Methodology for Face-to-Face-Bonded 3D ICs. ISPD 2021: 39-46 - [c170]Sai Surya Kiran Pentapati, Bon Woong Ku, Sung Kyu Lim
:
ML-Based Wire RC Prediction in Monolithic 3D ICs with an Application to Full-Chip Optimization. ISPD 2021: 75-82 - [c169]Lingjun Zhu, Sung Kyu Lim
:
Physical Design Challenges and Solutions for Emerging Heterogeneous 3D Integration Technologies. ISPD 2021: 127-134 - [c168]Jan Moritz Joseph
, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim
, Thilo Pionteck, Tushar Krishna:
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. ISQED 2021: 60-66 - [c167]Brian Crafton, Arijit Raychowdhury, Sung Kyu Lim
:
Automatic Generation of Translators for Packet-Based and Emerging Protocols. ISQED 2021: 488-495 - [i4]Matheus A. Cavalcante, Anthony Agnesina, Samuel Riedel, Moritz Brunion, Alberto García-Ortiz, Dragomir Milojevic, Francky Catthoor, Sung Kyu Lim, Luca Benini:
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration. CoRR abs/2112.01168 (2021) - 2020
- [j80]Lingjun Zhu
, Lennart Bamberg
, Anthony Agnesina
, Francky Catthoor, Dragomir Milojevic
, Manu Komalan, Julien Ryckaert, Alberto García-Ortiz
, Sung Kyu Lim
:
Heterogeneous 3D Integration for a RISC-V System With STT-MRAM. IEEE Comput. Archit. Lett. 19(1): 51-54 (2020) - [j79]Arjun Chaudhuri
, Sanmitra Banerjee
, Heechun Park, Jinwoo Kim
, Gauthaman Murali
, Edward Lee
, Daehyun Kim
, Sung Kyu Lim
, Saibal Mukhopadhyay, Krishnendu Chakrabarty
:
Advances in Design and Test of Monolithic 3-D ICs. IEEE Des. Test 37(4): 92-100 (2020) - [j78]Bon Woong Ku
, Kyungwook Chang
, Sung Kyu Lim
:
Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-Level 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1151-1164 (2020) - [j77]Anthony Agnesina
, Sung Kyu Lim
, Etienne Lepercq, Jose Escobedo Del Cid:
Improving FPGA-Based Logic Emulation Systems through Machine Learning. ACM Trans. Design Autom. Electr. Syst. 25(5): 46:1-46:20 (2020) - [j76]Anthony Agnesina
, James Yamaguchi, Christian Krutzik, John Carson, Jean Yang-Scharlotta
, Sung Kyu Lim
:
A COTS-Based Novel 3-D DRAM Memory Cube Architecture for Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 28(9): 2055-2068 (2020) - [j75]Jinwoo Kim
, Gauthaman Murali
, Heechun Park
, Eric Qin, Hyoukjun Kwon
, Venkata Chaitanya Krishna Chekuri
, Nael Mizanur Rahman, Nihar Dasari, Arvind Singh, Minah Lee
, Hakki Mert Torun
, Kallol Roy
, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, Sung Kyu Lim
:
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse. IEEE Trans. Very Large Scale Integr. Syst. 28(11): 2424-2437 (2020) - [c166]Shao-Chun Hung, Yi-Chen Lu, Sung Kyu Lim
, Krishnendu Chakrabarty
:
Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs *. ATS 2020: 1-6 - [c165]Yi-Chen Lu, Sai Surya Kiran Pentapati, Lingjun Zhu, Kambiz Samadi, Sung Kyu Lim
:
TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs. DAC 2020: 1-6 - [c164]Lennart Bamberg
, Alberto García Ortiz, Lingjun Zhu, Sai Pentapati, Da Eun Shim, Sung Kyu Lim:
Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs. DATE 2020: 37-42 - [c163]Sai Surya Kiran Pentapati, Kyungwook Chang, Vassilios Gerousis, Rwik Sengupta, Sung Kyu Lim
:
Pin-3D: A Physical Synthesis and Post-Layout Optimization Flow for Heterogeneous Monolithic 3D ICs. ICCAD 2020: 4:1-4:9 - [c162]Jinwoo Kim, Gauthaman Murali
, Pruek Vanna-Iampikul
, Edward Lee, Daehyun Kim, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty
, Saibal Mukhopadhyay, Sung Kyu Lim
:
RTL-to-GDS Design Tools for Monolithic 3D ICs. ICCAD 2020: 126:1-126:8 - [c161]Anthony Agnesina, Kyungwook Chang, Sung Kyu Lim
:
VLSI Placement Parameter Optimization using Deep Reinforcement Learning. ICCAD 2020: 144:1-144:9 - [c160]Yi-Chen Lu, Siddhartha Nath, Sai Surya Kiran Pentapati, Sung Kyu Lim
:
A Fast Learning-Driven Signoff Power Optimization Framework. ICCAD 2020: 161:1-161:9 - [c159]Jinwoo Kim, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman, Majid Ahadi Dolatsara, Hakki Mert Torun, Madhavan Swaminathan, Saibal Mukhopadhyay, Sung Kyu Lim:
Silicon vs. Organic Interposer: PPA and Reliability Tradeoffs in Heterogeneous 2.5D Chiplet Integration. ICCD 2020: 80-87 - [c158]Anthony Agnesina, Da Eun Shim, James Yamaguchi, Christian Krutzik, John Carson, Dan Nakamura, Sung Kyu Lim
:
A Fault-Tolerant and High-Speed Memory Controller Targeting 3D Flash Memory Cubes for Space Applications. ICCD 2020: 425-432 - [c157]Bon Woong Ku, Sung Kyu Lim
:
Pin-in-the-middle: an efficient block pin assignment methodology for block-level monolithic 3D ICs. ISLPED 2020: 85-90 - [c156]Lingjun Zhu
, Kyungwook Chang, Dusan Petranovic, Saurabh Sinha, Yun Seop Yu, Sung Kyu Lim
:
Full-Chip Electro-Thermal Coupling Extraction and Analysis for Face-to-Face Bonded 3D ICs. ISPD 2020: 39-46 - [c155]Heechun Park, Bon Woong Ku, Kyungwook Chang, Da Eun Shim, Sung Kyu Lim
:
Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs. ISPD 2020: 47-54 - [c154]Brian Crafton, Samuel Spetalnick, Gauthaman Murali
, Tushar Krishna, Sung Kyu Lim
, Arijit Raychowdhury:
Breaking Barriers: Maximizing Array Utilization for Compute in-Memory Fabrics. VLSI-SOC 2020: 123-128 - [c153]Brian Crafton, Samuel Spetalnick, Gauthaman Murali
, Tushar Krishna, Sung Kyu Lim
, Arijit Raychowdhury:
Statistical Array Allocation and Partitioning for Compute In-Memory Fabrics. VLSI-SoC (Selected Papers) 2020: 323-341 - [i3]Fares Elsabbagh, Blaise Tine, Priyadarshini Roshan, Ethan Lyons, Euna Kim, Da Eun Shim, Lingjun Zhu, Sung Kyu Lim, Hyesoon Kim:
Vortex: OpenCL Compatible RISC-V GPGPU. CoRR abs/2002.12151 (2020) - [i2]Brian Crafton, Samuel Spetalnick, Gauthaman Murali
, Tushar Krishna, Sung Kyu Lim, Arijit Raychowdhury:
Breaking Barriers: Maximizing Array Utilization for Compute In-Memory Fabrics. CoRR abs/2008.06741 (2020) - [i1]Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim, Thilo Pionteck, Tushar Krishna:
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. CoRR abs/2012.12563 (2020)
2010 – 2019
- 2019
- [j74]Sai Pentapati, Lingjun Zhu
, Lennart Bamberg
, Da Eun Shim, Alberto García Ortiz
, Sung Kyu Lim
:
A Logic-on-Memory Processor-System Design With Monolithic 3-D Technology. IEEE Micro 39(6): 38-45 (2019) - [j73]Tianchen Wang
, Sandeep Kumar Samal
, Sung Kyu Lim
, Yiyu Shi:
Entropy Production-Based Full-Chip Fatigue Analysis: From Theory to Mobile Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(1): 84-95 (2019) - [j72]Kyungwook Chang
, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
:
System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 888-898 (2019) - [c152]Heechun Park, Kyungwook Chang, Bon Woong Ku, Jinwoo Kim, Edward Lee, Daehyun Kim, Arjun Chaudhuri, Sanmitra Banerjee, Saibal Mukhopadhyay, Krishnendu Chakrabarty
, Sung Kyu Lim
:
RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs. DAC 2019: 101 - [c151]Jinwoo Kim, Gauthaman Murali
, Heechun Park, Eric Qin, Hyoukjun Kwon
, Venkata Chaitanya Krishna Chekuri
, Nihar Dasari, Arvind Singh, Minah Lee
, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, Sung Kyu Lim
:
Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse. DAC 2019: 178 - [c150]Arjun Chaudhuri, Sanmitra Banerjee, Heechun Park, Bon Woong Ku, Krishnendu Chakrabarty
, Sung Kyu Lim
:
Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs. ETS 2019: 1-6 - [c149]Sai Surya Kiran Pentapati, Da Eun Shim, Sung Kyu Lim
:
Logic Monolithic 3D ICs: PPA Benefits and EDA Tools Necessary. ACM Great Lakes Symposium on VLSI 2019: 445-450 - [c148]Anthony Agnesina, Etienne Lepercq, Jose Escobedo, Sung Kyu Lim
:
Reducing Compilation Effort in Commercial FPGA Emulation Systems Using Machine Learning. ICCAD 2019: 1-8 - [c147]Yi-Chen Lu, Jeehyun Lee, Anthony Agnesina, Kambiz Samadi, Sung Kyu Lim
:
GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization. ICCAD 2019: 1-8 - [c146]Hakki Mert Torun, Huan Yu, Nihar Dasari, Venkata Chaitanya Krishna Chekuri
, Arvind Singh, Jinwoo Kim, Sung Kyu Lim
, Saibal Mukhopadhyay, Madhavan Swaminathan:
A Spectral Convolutional Net for Co-Optimization of Integrated Voltage Regulators and Embedded Inductors. ICCAD 2019: 1-8 - [c145]Da Eun Shim, Sai Pentapati, Jeehyun Lee, Yun Seop Yu, Sung Kyu Lim:
Tier Partitioning and Flip-flop Relocation Methods for Clock Trees in Monolithic 3D ICs. ISLPED 2019: 1-6 - 2018
- [j71]Kyungwook Chang
, Deepak Kadetotad, Yu Cao
, Jae-sun Seo, Sung Kyu Lim:
Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition. ACM J. Emerg. Technol. Comput. Syst. 14(4): 42:1-42:19 (2018) - [c144]Anthony Agnesina, Amanvir Sidana, James Yamaguchi, Christian Krutzik, John Carson, Jean Yang-Scharlotta, Sung Kyu Lim
:
A novel 3D DRAM memory cube architecture for space applications. DAC 2018: 24:1-24:6 - [c143]Bon Woong Ku, Yu Liu, Yingyezhe Jin, Sandeep Kumar Samal, Peng Li, Sung Kyu Lim
:
Design and architectural co-optimization of monolithic 3D liquid state machine-based neuromorphic processor. DAC 2018: 165:1-165:6 - [c142]Pu Pang, Yixun Zhang, Tianjian Li, Sung Kyu Lim
, Quan Chen, Xiaoyao Liang, Li Jiang:
In-growth test for monolithic 3D integrated SRAM. DATE 2018: 569-572 - [c141]Bon Woong Ku, Yu Liu, Yingyezhe Jin, Peng Li, Sung Kyu Lim
:
Area-efficient and low-power face-to-face-bonded 3D liquid state machine design. ICCAD 2018: 121 - [c140]Kyungwook Chang, Sai Pentapati, Da Eun Shim, Sung Kyu Lim
:
Road to High-Performance 3D ICs: Performance Optimization Methodologies for Monolithic 3D ICs. ISLPED 2018: 33:1-33:6 - [c139]Bon Woong Ku, Kyungwook Chang, Sung Kyu Lim
:
Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs. ISPD 2018: 90-97 - [c138]Md Musabbir Adnan, Sagarvarma Sayyaparaju, Garrett S. Rose
, Catherine D. Schuman
, Bon Woong Ku, Sung Kyu Lim
:
A Twin Memristor Synapse for Spike Timing Dependent Learning in Neuromorphic Systems. SoCC 2018: 37-42 - 2017
- [j70]Sandeep Kumar Samal
, Guoqing Chen, Sung Kyu Lim
:
Improving Performance under Process and Voltage Variations in Near-Threshold Computing Using 3D ICs. ACM J. Emerg. Technol. Comput. Syst. 13(4): 59:1-59:18 (2017) - [j69]Sung Kyu Lim
:
Bringing 3D ICs to Aerospace: Needs for Design Tools and Methodologies. J. Inform. and Commun. Convergence Engineering 15(2) (2017) - [j68]Seung-Ho Ok, Yong-Hwan Lee, Jae Hoon Shim, Sung Kyu Lim
, Byungin Moon
:
The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors. Sensors 17(2): 426 (2017) - [j67]Sandeep Kumar Samal
, Kambiz Samadi, Pratyush Kamal, Yang Du, Sung Kyu Lim
:
Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(6): 992-1003 (2017) - [j66]Shreepad Panth
, Sandeep Kumar Samal
, Kambiz Samadi, Yang Du, Sung Kyu Lim
:
Tier Degradation of Monolithic 3-D ICs: A Power Performance Study at Different Technology Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(8): 1265-1273 (2017) - [j65]Tiantao Lu
, Caleb Serafy, Zhiyuan Yang, Sandeep Kumar Samal
, Sung Kyu Lim
, Ankur Srivastava
:
TSV-Based 3-D ICs: Design Methods and Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(10): 1593-1619 (2017) - [j64]Shreepad Panth
, Kambiz Samadi, Yang Du, Sung Kyu Lim
:
Shrunk-2-D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(10): 1716-1724 (2017) - [j63]Jaewon Jang, Minho Cheong, Jin-Ho Ahn, Sung Kyu Lim
, Sungho Kang
:
Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1178-1182 (2017) - [j62]Moongon Jung
, Taigon Song, Yarui Peng
, Sung Kyu Lim
:
Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning. IEEE Trans. Very Large Scale Integr. Syst. 25(7): 2109-2117 (2017) - [j61]Kyungwook Chang
, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
:
Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node. IEEE Trans. Very Large Scale Integr. Syst. 25(7): 2118-2129 (2017) - [c137]Kyungwook Chang, Abhishek Koneru, Krishnendu Chakrabarty
, Sung Kyu Lim
:
Design automation and testing of monolithic 3D ICs: Opportunities, challenges, and solutions: (Invited paper). ICCAD 2017: 805-810 - [c136]Kyungwook Chang, Bon Woong Ku, Saurabh Sinha, Sung Kyu Lim
:
Full-chip monolithic 3D IC design and power performance analysis with ASAP7 library: (Invited Paper). ICCAD 2017: 1005-1010 - [c135]Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
:
Frequency and time domain analysis of power delivery network for monolithic 3D ICs. ISLPED 2017: 1-6 - [c134]Kyungwook Chang, Deepak Kadetotad, Yu Cao
, Jae-sun Seo, Sung Kyu Lim
:
Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition. ISLPED 2017: 1-6 - [c133]Bon Woong Ku, Taigon Song, Arthur Nieuwoudt, Sung Kyu Lim
:
Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity. ISLPED 2017: 1-6 - [c132]Sandeep Kumar Samal, Sourabh Khandelwal
, Asif Islam Khan, Sayeef S. Salahuddin, Chenming Hu, Sung Kyu Lim
:
Full chip power benefits with negative capacitance FETs. ISLPED 2017: 1-6 - [c131]Austin Wyer, Md Musabbir Adnan, Bon Woong Ku, Sung Kyu Lim
, Catherine D. Schuman
, Raphael C. Pooser, Garrett S. Rose
:
Evaluating online-learning in memristive neuromorphic circuits. NCS 2017: 5:1-5:8 - 2016
- [j60]Daehyun Kim, Sung Kyu Lim
:
Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools - Part 2. IEEE Des. Test 33(2): 7-8 (2016) - [j59]Lalinthip Tangjittaweechai, Mongkol Ekpanyapong, Thaisiri Watewai, Krit Athikulwongse, Sung Kyu Lim
, Adriano Tavares
:
Fast bidirectional shortest path on GPU. IEICE Electron. Express 13(6): 20160036 (2016) - [j58]Yun Seop Yu, Sung Kyu Lim:
Device Coupling Effects of Monolithic 3D Inverters. J. Inform. and Commun. Convergence Engineering 14(1) (2016) - [j57]Sandeep Kumar Samal, Guoqing Chen, Sung Kyu Lim:
Machine Learning Based Variation Modeling and Optimization for 3D ICs. J. Inform. and Commun. Convergence Engineering 14(4) (2016) - [j56]Young-Ho Gong, Jae Min Kim, Sung Kyu Lim
, Sung Woo Chung:
Exploration of temperature-aware refresh schemes for 3D stacked eDRAM caches. Microprocess. Microsystems 42: 100-112 (2016) - [j55]Hourieh Attarzadeh, Sung Kyu Lim
, Trond Ytterdal:
Design and Analysis of a Stochastic Flash Analog-to-Digital Converter in 3D IC technology for integration with ultrasound transducer array. Microelectron. J. 48: 39-49 (2016) - [j54]Sandeep Kumar Samal, Shreepad Panth, Kambiz Samadi, Mehdi Saedi, Yang Du, Sung Kyu Lim
:
Adaptive Regression-Based Thermal Modeling and Optimization for Monolithic 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1707-1720 (2016) - [j53]Taigon Song
, Shreepad Panth, Yoo-Jin Chae, Sung Kyu Lim
:
More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2056-2067 (2016) - [j52]Taigon Song, Chang Liu, Yarui Peng
, Sung Kyu Lim
:
Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1636-1648 (2016) - [c130]Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
:
Match-making for monolithic 3D IC: finding the right technology node. DAC 2016: 77:1-77:6 - [c129]Bon Woong Ku, Peter Debacker, Dragomir Milojevic
, Praveen Raghavan, Sung Kyu Lim
:
How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node? ICCAD 2016: 87 - [c128]Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Sung Kyu Lim
:
Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs. ICCAD 2016: 129 - [c127]Kyungwook Chang, Saurabh Sinha, Brian Cline, Raney Southerland, Michael Doherty, Greg Yeric, Sung Kyu Lim
:
Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools. ICCAD 2016: 130 - [c126]Kwang Min Kim, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
:
Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study. ISLPED 2016: 70-75 - [c125]Bon Woong Ku, Peter Debacker, Dragomir Milojevic
, Praveen Raghavan, Diederik Verkest, Aaron Thean, Sung Kyu Lim
:
Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs. ISLPED 2016: 76-81 - [c124]Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Sung Kyu Lim
:
How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD Solutions. ISLPED 2016: 320-325 - [c123]Kartik Acharya, Kyungwook Chang, Bon Woong Ku, Shreepad Panth, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
:
Monolithic 3D IC design: Power, performance, and area impact at 7nm. ISQED 2016: 41-48 - 2015
- [j51]Dae Hyun Kim, Sung Kyu Lim
:
Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools. IEEE Des. Test 32(4): 6-7 (2015) - [j50]Dae Hyun Kim, Sung Kyu Lim
:
Physical Design and CAD Tools for 3-D Integrated Circuits: Challenges and Opportunities. IEEE Des. Test 32(4): 8-22 (2015) - [j49]Taigon Song, Sung Kyu Lim:
Die-to-Die Parasitic Extraction Targeting Face-to-Face Bonded 3D ICs. J. Inform. and Commun. Convergence Engineering 13(3) (2015) - [j48]Taigon Song, Sung Kyu Lim:
Full-Chip Power/Performance Benefits of Carbon Nanotube-Based Circuits. J. Inform. and Commun. Convergence Engineering 13(3) (2015) - [j47]Daehyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
:
Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory). IEEE Trans. Computers 64(1): 112-125 (2015) - [j46]Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim
:
Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 540-553 (2015) - [j45]Yarui Peng
, Dusan Petranovic, Sung Kyu Lim
:
Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(12): 1964-1976 (2015) - [j44]Brandon Noia, Shreepad Panth, Krishnendu Chakrabarty
, Sung Kyu Lim
:
Scan Test of Die Logic in 3-D ICs Using TSV Probing. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 317-330 (2015) - [c122]Neela Lohith Penmetsa, Christos P. Sotiriou, Sung Kyu Lim
:
Low Power Monolithic 3D IC Design of Asynchronous AES Core. ASYNC 2015: 93-99 - [c121]Yarui Peng
, Bon Woong Ku, Youn-Sik Park, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi, Sung Kyu Lim
:
Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM. DAC 2015: 91:1-91:6 - [c120]Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim
:
Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications. DAC 2015: 92:1-92:6 - [c119]Yarui Peng
, Taigon Song, Dusan Petranovic, Sung Kyu Lim
:
Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs. ICCAD 2015: 649-655 - [c118]Tianchen Wang, Sandeep Kumar Samal, Sung Kyu Lim
, Yiyu Shi:
A Novel Entropy Production Based Full-Chip TSV Fatigue Analysis. ICCAD 2015: 744-751 - [c117]Taigon Song, Shreepad Panth, Yoo-Jin Chae, Sung Kyu Lim
:
Three-Tier 3D ICs for More Power Reduction: Strategies in CAD, Design, and Bonding Selection. ICCAD 2015: 752-757 - [c116]Hourieh Attarzadeh, Sung Kyu Lim
, Trond Ytterdal:
Stacking integration methodologies in 3D IC for 3D ultrasound image processing application: A stochastic flash ADC design case study. ISCAS 2015: 1266-1269 - [c115]Kyungwook Chang, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
:
Power benefit study of monolithic 3D IC at the 7nm technology node. ISLPED 2015: 201-206 - [c114]Li Jiang, Pu Pang, Naifeng Jing, Sung Kyu Lim
, Xiaoyao Liang, Qiang Xu
:
On diagnosable and tunable 3D clock network design for lifetime reliability enhancement. ITC 2015: 1-10 - 2014
- [j43]Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Kyu Lim
:
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC. Commun. ACM 57(1): 107-115 (2014) - [j42]Sung Kyu Lim:
Research Needs for TSV-Based 3D IC Architectural Floorplanning. J. Inform. and Commun. Convergence Engineering 12(1): 46-52 (2014) - [j41]Shreepad Panth, Sandeep Kumar Samal, Yun Seop Yu, Sung Kyu Lim:
Design Challenges and Solutions for Ultra-High-Density Monolithic 3D ICs. J. Inform. and Commun. Convergence Engineering 12(3): 186-192 (2014) - [j40]Chang-Chih Chen, Muhammad Bashir, Linda S. Milor
, Daehyun Kim, Sung Kyu Lim:
Simulation of system backend dielectric reliability. Microelectron. J. 45(10): 1327-1334 (2014) - [j39]Daehyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim
:
TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(9): 1384-1395 (2014) - [j38]Jiwoo Pak, Sung Kyu Lim
, David Z. Pan:
Electromigration Study for Multiscale Power/Ground Vias in TSV-Based 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1873-1885 (2014) - [j37]Yarui Peng
, Taigon Song, Dusan Petranovic, Sung Kyu Lim
:
Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1900-1913 (2014) - [j36]Muhammad Muqarrab Bashir, Chang-Chih Chen, Linda Milor
, Dae Hyun Kim, Sung Kyu Lim
:
Backend Dielectric Reliability Full Chip Simulator. IEEE Trans. Very Large Scale Integr. Syst. 22(8): 1750-1762 (2014) - [j35]Krit Athikulwongse, Mongkol Ekpanyapong, Sung Kyu Lim
:
Exploiting Die-to-Die Thermal Coupling in 3-D IC Placement. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2145-2155 (2014) - [c113]Moongon Jung, Taigon Song, Yang Wan, Yarui Peng
, Sung Kyu Lim
:
On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective. DAC 2014: 4:1-4:6 - [c112]Yarui Peng, Dusan Petranovic, Sung Kyu Lim:
Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling. DAC 2014: 28:1-28:6 - [c111]Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim
:
Power-Performance Study of Block-Level Monolithic 3D-ICs Considering Inter-Tier Performance Variations. DAC 2014: 62:1-62:6 - [c110]Sandeep Kumar Samal, Shreepad Panth, Kambiz Samadi, Mehdi Saedi, Yang Du, Sung Kyu Lim
:
Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs. DAC 2014: 206:1-206:6 - [c109]Young-Joon Lee, Sung Kyu Lim:
On GPU bus power reduction with 3D IC technologies. DATE 2014: 1-6 - [c108]Sandeep Kumar Samal, Kambiz Samadi, Pratyush Kamal, Yang Du, Sung Kyu Lim
:
Full chip impact study of power delivery network designs in monolithic 3D ICs. ICCAD 2014: 565-572 - [c107]Shreepad A. Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim
:
Design and CAD methodologies for low power gate-level monolithic 3D ICs. ISLPED 2014: 171-176 - [c106]Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim
:
Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs. ISPD 2014: 47-54 - 2013
- [j34]Krit Athikulwongse, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim
:
Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(6): 905-917 (2013) - [j33]Moongon Jung, David Z. Pan, Sung Kyu Lim
:
Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11): 1694-1707 (2013) - [j32]Sai Manoj Pudukotai Dinakarrao
, Hao Yu
, Yang Shang, Chuan Seng Tan
, Sung Kyu Lim
:
Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical-Thermal-Mechanical Coupling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11): 1734-1747 (2013) - [j31]Young-Joon Lee, Sung Kyu Lim
:
Ultrahigh Density Logic Designs Using Monolithic 3-D Integration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(12): 1892-1905 (2013) - [j30]Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim
:
Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout. IEEE Trans. Very Large Scale Integr. Syst. 21(5): 862-874 (2013) - [j29]Junghee Lee
, Chrysostomos Nicopoulos
, Hyung Gyu Lee, Shreepad Panth, Sung Kyu Lim
, Jongman Kim:
IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures. IEEE Trans. Very Large Scale Integr. Syst. 21(6): 1080-1093 (2013) - [c105]Shreepad Panth, Kambiz Samadi, Sung Kyu Lim
:
Test-TSV estimation during 3D-IC partitioning. 3DIC 2013: 1-7 - [c104]Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim
:
High-density integration of functional modules using monolithic 3D-IC technology. ASP-DAC 2013: 681-686 - [c103]Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, Sung Kyu Lim
:
Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs. ASP-DAC 2013: 687-692 - [c102]Yang Shang, Chun Zhang, Hao Yu, Chuan Seng Tan
, Xin Zhao, Sung Kyu Lim
:
Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model. ASP-DAC 2013: 693-698 - [c101]Moongon Jung, Taigon Song, Yang Wan, Young-Joon Lee, Debabrata Mohapatra, Hong Wang, Greg Taylor, Devang Jariwala, Vijay Pitchumani, Patrick Morrow, Clair Webb, Paul Fischer, Sung Kyu Lim
:
How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core. CICC 2013: 1-4 - [c100]Young-Joon Lee, Daniel B. Limbrick
, Sung Kyu Lim
:
Power benefit study for ultra-high density transistor-level monolithic 3D ICs. DAC 2013: 104:1-104:10 - [c99]Taigon Song, Chang Liu, Yarui Peng
, Sung Kyu Lim
:
Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs. DAC 2013: 180:1-180:7 - [c98]Yarui Peng
, Taigon Song, Dusan Petranovic, Sung Kyu Lim
:
On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs. ICCAD 2013: 281-288 - [c97]Xin Zhao, Yang Wan, Michael Scheuermann, Sung Kyu Lim
:
Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs. ICCAD 2013: 363-370 - [c96]Chun Zhang, Moongon Jung, Sung Kyu Lim
, Yiyu Shi:
Novel crack sensor for TSV-based 3D integrated circuits: design and deployment perspectives. ICCAD 2013: 371-378 - [c95]Jiwoo Pak, Sung Kyu Lim
, David Z. Pan:
Electromigration study for multi-scale power/ground vias in TSV-based 3D ICs. ICCAD 2013: 379-386 - [c94]Seung-Ho Ok, Kyeong-Ryeol Bae, Sung Kyu Lim
, Byungin Moon:
Design and analysis of 3D IC-based low power stereo matching processors. ISLPED 2013: 15-20 - [c93]Sandeep Kumar Samal, Yarui Peng
, Yang Zhang, Sung Kyu Lim
:
Design and analysis of ultra low power processors using sub/near-threshold 3D stacked ICs. ISLPED 2013: 21-26 - 2012
- [j28]Dae Hyun Kim, Sung Kyu Lim
:
Design Quality Trade-Off Studies for 3-D ICs Built With Sub-Micron TSVs and Future Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 240-248 (2012) - [j27]Chang-Chih Chen, Fahad Ahmed, Dae Hyun Kim, Sung Kyu Lim
, Linda Milor
:
Backend dielectric reliability simulator for microprocessor system. Microelectron. Reliab. 52(9-10): 1953-1959 (2012) - [j26]Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Kyu Lim
:
TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(8): 1194-1207 (2012) - [j25]Xin Zhao, Jeremy R. Tolbert, Saibal Mukhopadhyay, Sung Kyu Lim
:
Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(8): 1222-1234 (2012) - [j24]Michael B. Healy, Sung Kyu Lim
:
Distributed TSV Topology for 3-D Power-Supply Networks. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 2066-2079 (2012) - [c92]Dae Hyun Kim, Rasit Onur Topaloglu
, Sung Kyu Lim
:
Block-level 3D IC design with through-silicon-via planning. ASP-DAC 2012: 335-340 - [c91]Xin Zhao, Sung Kyu Lim
:
Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs. ASP-DAC 2012: 347-352 - [c90]David Z. Pan, Sung Kyu Lim
, Krit Athikulwongse, Moongon Jung, Joydeep Mitra, Jiwoo Pak, Mohit Pathak, Jae-Seok Yang:
Design for manufacturability and reliability for TSV-based 3D ICs. ASP-DAC 2012: 750-755 - [c89]Sergej Deutsch, Krishnendu Chakrabarty
, Shreepad Panth, Sung Kyu Lim
:
TSV Stress-Aware ATPG for 3D Stacked ICs. Asian Test Symposium 2012: 31-36 - [c88]Young-Joon Lee, Inki Hong, Sung Kyu Lim
:
Slew-aware buffer insertion for through-silicon-via-based 3D ICs. CICC 2012: 1-8 - [c87]Xin Zhao, Michael Scheuermann, Sung Kyu Lim
:
Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs. DAC 2012: 157-162 - [c86]Moongon Jung, David Z. Pan, Sung Kyu Lim
:
Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs. DAC 2012: 317-326 - [c85]Krit Athikulwongse, Mohit Pathak, Sung Kyu Lim
:
Exploiting die-to-die thermal coupling in 3D IC placement. DAC 2012: 741-746 - [c84]Jiwoo Pak, Sung Kyu Lim
, David Z. Pan:
Electromigration-aware routing for 3D ICs with stress-aware EM modeling. ICCAD 2012: 325-332 - [c83]Young-Joon Lee, Patrick Morrow, Sung Kyu Lim
:
Ultra high density logic designs using transistor-level monolithic 3D integration. ICCAD 2012: 539-546 - [c82]Xin Zhao, Sung Kyu Lim
:
TSV array utilization in low-power 3D clock network design. ISLPED 2012: 21-26 - [c81]Young-Joon Lee, Sung Kyu Lim
:
Fast delay estimation with buffer insertion for through-silicon-via-based 3D interconnects. ISQED 2012: 228-335 - [c80]Chang Liu, Sung Kyu Lim
:
A design tradeoff study with monolithic 3D integration. ISQED 2012: 529-536 - [c79]Kaiyuan Yang
, Dae Hyun Kim, Sung Kyu Lim
:
Design quality tradeoff studies for 3D ICs built with nano-scale TSVs and devices. ISQED 2012: 740-746 - [c78]Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
:
3D-MAPS: 3D Massively parallel processor with stacked memory. ISSCC 2012: 188-190 - [c77]Brandon Noia, Shreepad Panth, Krishnendu Chakrabarty
, Sung Kyu Lim
:
Scan test of die logic in 3D ICs using TSV probing. ITC 2012: 1-8 - [c76]Shreepad Panth, Sung Kyu Lim
:
Transition delay fault testing of 3D ICs with IR-drop study. VTS 2012: 270-275 - 2011
- [j23]Muhammad Bashir, Linda Milor
, Dae Hyun Kim, Sung Kyu Lim
:
Impact of irregular geometries on low-k dielectric breakdown. Microelectron. Reliab. 51(9-11): 1582-1586 (2011) - [j22]Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim
:
Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(5): 732-745 (2011) - [j21]Jeremy R. Tolbert, Xin Zhao, Sung Kyu Lim
, Saibal Mukhopadhyay:
Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(9): 1349-1358 (2011) - [j20]Young-Joon Lee, Sung Kyu Lim
:
Co-Optimization and Analysis of Signal, Power, and Thermal Interconnects in 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1635-1648 (2011) - [j19]Michael B. Healy, Fayez Mohamood, Hsien-Hsin S. Lee, Sung Kyu Lim
:
Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation. ACM Trans. Design Autom. Electr. Syst. 16(4): 46:1-46:25 (2011) - [c75]Jae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim
, David Z. Pan:
Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs. ASP-DAC 2011: 621-626 - [c74]Moongon Jung, Joydeep Mitra, David Z. Pan, Sung Kyu Lim
:
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC. DAC 2011: 188-193 - [c73]Chang Liu, Taigon Song, Jonghyun Cho, Joohee Kim, Joungho Kim, Sung Kyu Lim
:
Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC. DAC 2011: 783-788 - [c72]Michael B. Healy, Sung Kyu Lim:
A novel TSV topology for many-tier 3D power-delivery networks. DATE 2011: 261-264 - [c71]Mohit Pathak, Jiwoo Pak, David Z. Pan, Sung Kyu Lim
:
Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs. ICCAD 2011: 555-562 - [c70]Moongon Jung, Xi Liu, Suresh K. Sitaraman, David Z. Pan, Sung Kyu Lim
:
Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC. ICCAD 2011: 563-570 - [c69]Dean L. Lewis, Shreepad Panth, Xin Zhao, Sung Kyu Lim
, Hsien-Hsin S. Lee:
Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores. ICCD 2011: 90-95 - [c68]Xin Zhao, Jeremy R. Tolbert, Chang Liu, Saibal Mukhopadhyay, Sung Kyu Lim:
Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits. ISLPED 2011: 9-14 - [c67]Dae Hyun Kim, Rasit Onur Topaloglu
, Sung Kyu Lim
:
TSV density-driven global placement for 3D stacked ICs. ISOCC 2011: 135-138 - [c66]Chang Liu, Taigon Song, Sung Kyu Lim
:
Signal integrity analysis and optimization for 3D ICs. ISQED 2011: 42-49 - [c65]Taigon Song, Chang Liu, Dae Hyun Kim, Sung Kyu Lim
, Jonghyun Cho, Joohee Kim, Junso Pak, Seungyoung Ahn, Joungho Kim, Kihyun Yoon:
Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs. ISQED 2011: 122-128 - [c64]Michael B. Healy, Sung Kyu Lim
:
Power-supply-network design in 3D integrated systems. ISQED 2011: 223-228 - [c63]Daehyun Kim, Suyoun Kim, Sung Kyu Lim
:
Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designs. SLIP 2011: 1-8 - [c62]Shreepad Panth, Sung Kyu Lim
:
Scan chain and power delivery network synthesis for pre-bond test of 3D ICs. VTS 2011: 26-31 - 2010
- [j18]Jae Sub Oh, Kwang Il Choi, Young Su Kim, Min Ho Kang, Myeong Ho Song, Sung Kyu Lim
, Dong Eun Yoo, Jeong Gyu Park, Hi Deok Lee, Ga Won Lee
:
SONOS-Type Flash Memory with HfO2 Thinner than 4 nm as Trapping Layer Using Atomic Layer Deposition. IEICE Trans. Electron. 93-C(5): 590-595 (2010) - [j17]Muhammad Bashir, Linda S. Milor
, Dae Hyun Kim, Sung Kyu Lim
:
Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown. Microelectron. Reliab. 50(9-11): 1341-1346 (2010) - [c61]Moongon Jung, Sung Kyu Lim
:
A study of IR-drop noise issues in 3D ICs with through-silicon-vias. 3DIC 2010: 1-7 - [c60]Young-Joon Lee, Sung Kyu Lim
:
Timing analysis and optimization for 3D stacked multi-core microprocessors. 3DIC 2010: 1-7 - [c59]Xin Zhao, Sung Kyu Lim
:
Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs. ASP-DAC 2010: 175-180 - [c58]Krit Athikulwongse, Xin Zhao, Sung Kyu Lim
:
Buffered clock tree sizing for skew minimization under power and thermal budgets. ASP-DAC 2010: 474-479 - [c57]Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
:
Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory. CICC 2010: 1-4 - [c56]Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim
, David Z. Pan:
TSV stress aware timing analysis with applications to 3D-IC layout optimization. DAC 2010: 803-806 - [c55]Mohit Pathak, Young-Joon Lee, Thomas Moon, Sung Kyu Lim
:
Through-silicon-via management during 3D physical design: When to add and how many? ICCAD 2010: 387-394 - [c54]Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim
:
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study. ICCAD 2010: 669-674 - [c53]Minki Cho, Chang Liu, Dae Hyun Kim, Sung Kyu Lim
, Saibal Mukhopadhyay:
Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system. ICCAD 2010: 694-697 - [c52]Daehyun Kim, Sung Kyu Lim
:
Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs. SLIP 2010: 25-32
2000 – 2009
- 2009
- [j16]Mohit Pathak, Sung Kyu Lim
:
Performance and Thermal-Aware Steiner Routing for 3-D Stacked ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(9): 1373-1386 (2009) - [j15]I. Faik Baskaya, David V. Anderson, Sung Kyu Lim
:
Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing. IEEE Trans. Circuits Syst. II Express Briefs 56-II(7): 565-569 (2009) - [c51]Michael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, Sung Kyu Lim
:
Thermal optimization in multi-granularity multi-core floorplanning. ASP-DAC 2009: 43-48 - [c50]Young-Joon Lee, Yoon Jo Kim, Gang Huang, Muhannad S. Bakir, Yogendra K. Joshi, Andrei G. Fedorov, Sung Kyu Lim:
Co-design of signal, power, and thermal distribution networks for 3D ICs. DATE 2009: 610-615 - [c49]Ye Tao, Sung Kyu Lim:
Decoupling capacitor planning with analytical delay model on RLC power grid. DATE 2009: 839-844 - [c48]Faik Baskaya, David V. Anderson, Paul E. Hasler, Sung Kyu Lim
:
A generic reconfigurable array specification and programming environment (GRASPER). ECCTD 2009: 619-622 - [c47]Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim
:
Pre-bond testable low-power clock tree design for 3D stacked ICs. ICCAD 2009: 184-190 - [c46]Young-Joon Lee, Rohan Goel, Sung Kyu Lim
:
Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs. ICCAD 2009: 645-651 - [c45]Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim
:
A study of Through-Silicon-Via impact on the 3D stacked IC layout. ICCAD 2009: 674-680 - [c44]Jeremy R. Tolbert, Xin Zhao, Sung Kyu Lim
, Saibal Mukhopadhyay:
Slew-aware clock tree design for reliable subthreshold circuits. ISLPED 2009: 15-20 - [c43]Dae Hyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim
:
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs. SLIP 2009: 85-92 - 2008
- [c42]Dae Hyun Kim, Sung Kyu Lim
:
Bus-aware microarchitectural floorplanning. ASP-DAC 2008: 204-208 - [c41]Jacob R. Minz, Xin Zhao, Sung Kyu Lim
:
Buffered clock tree synthesis for 3D ICs under thermal variations. ASP-DAC 2008: 504-509 - [c40]Michael B. Healy, Fayez Mohamood, Hsien-Hsin S. Lee, Sung Kyu Lim
:
A unified methodology for power supply noise reduction in modern microarchitecture design. ASP-DAC 2008: 611-616 - [c39]Dae Hyun Kim, Sung Kyu Lim:
Global bus route optimization with application to microarchitectural design exploration. ICCD 2008: 658-663 - 2007
- [j14]Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim
, Hsien-Hsin S. Lee, Gabriel H. Loh:
Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1): 38-52 (2007) - [j13]Eric Wong, Jacob R. Minz, Sung Kyu Lim
:
Decoupling-Capacitor Planning and Sizing for Noise and Leakage Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 2023-2034 (2007) - [j12]Sung Kyu Lim, Massoud Pedram:
Introduction to special issue on demonstrable software systems and hardware platforms. ACM Trans. Design Autom. Electr. Syst. 12(3): 20:1-20:3 (2007) - [c38]Mongkol Ekpanyapong, Xin Zhao, Sung Kyu Lim
:
An Efficient Computation of Statistically Critical Sequential Paths Under Retiming. ASP-DAC 2007: 547-552 - [c37]Fayez Mohamood, Michael B. Healy, Sung Kyu Lim
, Hsien-Hsin S. Lee:
Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling. ASP-DAC 2007: 786-791 - [c36]I. Faik Baskaya, Brian Gestner, Christopher M. Twigg, Sung Kyu Lim, David V. Anderson, Paul E. Hasler:
Rapid Prototyping of Large-scale Analog Circuits With Field Programmable Analog Array. FCCM 2007: 319-320 - [c35]Mohit Pathak, Sung Kyu Lim
:
Thermal-aware Steiner routing for 3D stacked ICs. ICCAD 2007: 205-211 - [c34]Eric Wong, Sung Kyu Lim
:
Whitespace redistribution for thermal via insertion in 3D stacked ICs. ICCD 2007: 267-272 - [c33]Mohit Pathak, Souvik Mukherjee, Madhavan Swaminathan, Ege Engin
, Sung Kyu Lim
:
Placement and routing of RF embedded passive designs in LCP substrate. ICCD 2007: 273-279 - 2006
- [j11]Peter G. Sassone, Sung Kyu Lim
:
Traffic: a novel geometric algorithm for fast wire-optimized floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1075-1086 (2006) - [j10]Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim
:
Profile-guided microarchitectural floor planning for deep submicron processor design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1289-1300 (2006) - [j9]Jacob R. Minz, Sung Kyu Lim
:
Block-level 3-D Global Routing With an Application to 3-D Packaging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2248-2257 (2006) - [j8]Mongkol Ekpanyapong, Michael B. Healy, Sung Kyu Lim
:
Profile-Driven Instruction Mapping for Dataflow Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 3017-3025 (2006) - [j7]Eric Wong, Jacob R. Minz, Sung Kyu Lim
:
Multi-Objective Module Placement For 3-D System-On-Package. IEEE Trans. Very Large Scale Integr. Syst. 14(5): 553-557 (2006) - [j6]I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim
, David V. Anderson:
Placement for large-scale floating-gate field-programable analog arrays. IEEE Trans. Very Large Scale Integr. Syst. 14(8): 906-910 (2006) - [c32]Mongkol Ekpanyapong, Thaisiri Watewai, Sung Kyu Lim
:
Statistical Bellman-Ford algorithm with an application to retiming. ASP-DAC 2006: 959-964 - [c31]Jacob R. Minz, Somaskanda Thyagaraja, Sung Kyu Lim
:
Optical routing for 3D system-on-package. DATE 2006: 337-338 - [c30]Eric Wong, Sung Kyu Lim:
3D floorplanning with thermal vias. DATE 2006: 878-883 - [c29]Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh:
Microarchitectural floorplanning under performance and thermal tradeoff. DATE 2006: 1288-1293 - [c28]Eric Wong, Jacob R. Minz, Sung Kyu Lim
:
Decoupling capacitor planning and sizing for noise and leakage reduction. ICCAD 2006: 395-400 - [c27]Mongkol Ekpanyapong, Sung Kyu Lim
:
Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization. ISPD 2006: 142-148 - [c26]Fayez Mohamood, Michael B. Healy, Sung Kyu Lim
, Hsien-Hsin S. Lee:
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design. MICRO 2006: 3-14 - 2005
- [j5]Sung Kyu Lim
:
Physical Design for 3D System on Package. IEEE Des. Test Comput. 22(6): 532-539 (2005) - [j4]Ramprasad Ravichandran, Sung Kyu Lim
, Michael T. Niemier:
Automatic cell placement for quantum-dot cellular automata. Integr. 38(3): 541-548 (2005) - [j3]Sung Kyu Lim
, Ramprasad Ravichandran, Michael T. Niemier:
Partitioning and placement for buildable QCA circuits. ACM J. Emerg. Technol. Comput. Syst. 1(1): 50-72 (2005) - [c25]Ramprasad Ravichandran, Michael T. Niemier, Sung Kyu Lim:
Partitioning and placement for buildable QCA circuits. ASP-DAC 2005: 424-427 - [c24]Mongkol Ekpanyapong, Michael B. Healy, Sung Kyu Lim
:
Placement for configurable dataflow architecture. ASP-DAC 2005: 1127-1130 - [c23]Karthik Balakrishnan, Vidit Nanda, Siddharth Easwar, Sung Kyu Lim
:
Wire congestion and thermal aware 3D global placement. ASP-DAC 2005: 1131-1134 - [c22]Michael B. Healy, Mongkol Ekpanyapong, Sung Kyu Lim
:
MILP-based Placement and Routing for Dataflow Architecture. FPL 2005: 71-76 - [c21]I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim
, David V. Anderson:
Hierarchical Placement for Large-scale FPAA. FPL 2005: 421-426 - [c20]Brian Stephen Smith, Sung Kyu Lim
:
QCA channel routing with wire crossing minimization. ACM Great Lakes Symposium on VLSI 2005: 217-220 - [c19]Jacob R. Minz, Sung Kyu Lim
, Cheng-Kok Koh:
3D module placement for congestion and power noise reduction. ACM Great Lakes Symposium on VLSI 2005: 458-461 - [c18]Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim
, Hsien-Hsin S. Lee
:
Wire-driven microarchitectural design space exploration. ISCAS (2) 2005: 1867-1870 - [c17]I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim
, Tyson S. Hall, David V. Anderson:
Mapping algorithm for large-scale field programmable analog array. ISPD 2005: 152-158 - [c16]Jacob R. Minz, Eric Wong, Sung Kyu Lim:
Reliability-aware floorplanning for 3D circuits. SoCC 2005: 81-82 - 2004
- [j2]Jason Cong, Sung Kyu Lim
:
Edge separability-based circuit clustering with application to multilevel circuit partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(3): 346-357 (2004) - [j1]Jason Cong, Sung Kyu Lim
:
Retiming-based timing analysis with an application to mincut-based global placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12): 1684-1692 (2004) - [c15]Jacob R. Minz, Sung Kyu Lim:
Layer assignment for reliable system-on-package. ASP-DAC 2004: 31-37 - [c14]Mongkol Ekpanyapong, Sung Kyu Lim:
Performance-driven global placement via adaptive network characterization. ASP-DAC 2004: 137-142 - [c13]Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim
:
Profile-guided microarchitectural floorplanning for deep submicron processor design. DAC 2004: 634-639 - [c12]Jacob R. Minz, Mohit Pathak, Sung Kyu Lim
:
Net and Pin Distribution for 3D Package Global Routing. DATE 2004: 1410-1411 - [c11]Ramprasad Ravichandran, Nihal Ladiwala, Jean Nguyen, Michael T. Niemier, Sung Kyu Lim
:
Automatic cell placement for quantum-dot cellular automata. ACM Great Lakes Symposium on VLSI 2004: 332-337 - [c10]Mongkol Ekpanyapong, Karthik Balakrishnan, Vidit Nanda, Sung Kyu Lim:
Simultaneous delay and power optimization in global placement. ISCAS (5) 2004: 57-60 - [c9]Pun Hang Shiu, Ramprasad Ravichandran, Siddharth Easwar, Sung Kyu Lim:
Multi-layer floorplanning for reliable system-on-package. ISCAS (5) 2004: 69-72 - 2003
- [c8]Peter G. Sassone, Sung Kyu Lim:
A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning. ICCAD 2003: 74-80 - 2000
- [c7]Jason Cong, Sung Kyu Lim
:
Edge separability based circuit clustering with application to circuit partitioning. ASP-DAC 2000: 429-434 - [c6]Jason Cong, Sung Kyu Lim
:
Performance driven multiway partitioning. ASP-DAC 2000: 441-446 - [c5]Maogang Wang, Sung Kyu Lim, Jason Cong, Majid Sarrafzadeh:
Multi-way partitioning using bi-partition heuristics. ASP-DAC 2000: 667-672 - [c4]Jason Cong, Sung Kyu Lim
, Chang Wu:
Performance driven multi-level and multiway partitioning with retiming. DAC 2000: 274-279 - [c3]Jason Cong, Sung Kyu Lim
:
Physical Planning with Retiming. ICCAD 2000: 2-7
1990 – 1999
- 1998
- [c2]Jason Cong, Sung Kyu Lim
:
Multiway partitioning with pairwise movement. ICCAD 1998: 512-516 - 1997
- [c1]Jason Cong, Honching Peter Li, Sung Kyu Lim
, Toshiyuki Shibuya, Dongmin Xu:
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering. ICCAD 1997: 441-446
Coauthor Index
aka: Venkata Chaitanya Krishna Chekuri
aka: Alberto García-Ortiz
aka: Shreepad A. Panth
aka: Sai Surya Kiran Pentapati
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