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ORCIDJosep Rius 0001
Person information
- affiliation: Polytechnic University of Catalonia, Department of Electronic Engineering, Spain
Other persons with the same name
- Josep Rius 0002
![[0000-0003-2783-6230]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0003-2783-6230")
(aka: Josep M. Rius-Torrentó) — University of Lleida, Department of Computer Science, Spain
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2010 – 2019
- 2015
[j8]Josep Rius:
Supply Noise and Impedance of On-Chip Power Distribution Networks in ICs With Nonuniform Power Consumption and Interblock Decoupling Capacitors. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 993-1004 (2015)- 2013
- [j7]Josep Rius:
IR-Drop in On-Chip Power Distribution Networks of ICs With Nonuniform Power Consumption. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 512-522 (2013) - 2010
- [c14]Josep Rius:
A single conductive surface as communication media for networked devices. BODYNETS 2010: 52-58 - [c13]Josep Rius:
Two-dimensional communication of networked devices through a single conductive surface. INSS 2010: 115-122 - [c12]Josep Rius:
A method for detecting resistive opens in buses. IOLTS 2010: 187-189
2000 – 2009
- 2009
- [j6]Josep Rius, Maurice Meijer:
Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling Capacitors. IEEE J. Solid State Circuits 44(2): 484-494 (2009) - [c11]Josep Rius, Luis Elvira Villagra, Maurice Meijer:
A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits. ETS 2009: 135-140 - [c10]Pablo Maqueda, Josep Rius:
Analysis of the extra delay on interconnects caused by resistive opens and shorts. IOLTS 2009: 208-209 - 2006
- [j5]Josep Rius, Maurice Meijer, José Pineda de Gyvez:
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. J. Low Power Electron. 2(1): 80-86 (2006) - 2005
- [c9]Josep Rius, José Pineda de Gyvez, Maurice Meijer:
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits. PATMOS 2005: 187-196 - 2004
- [j4]Josep Rius Vázquez, José Pineda de Gyvez:
Built-in current sensor for ΔIDDQ testing. IEEE J. Solid State Circuits 39(3): 511-518 (2004) - [c8]Josep Rius Vázquez, José Pineda de Gyvez:
Power Supply Noise Monitor for Signal Integrity Faults. DATE 2004: 1406-1407 - [c7]Josep Rius Vázquez, José Pineda de Gyvez:
Built-in Current Sensor for ?I{DDQ} Testing of Deep Submicron Digital CMOS ICs. VTS 2004: 53-58 - [c6]Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras:
BIST Technique by Equally Spaced Test Vector Sequences. VTS 2004: 206-216 - 2003
- [c5]Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras:
On the selection of efficient arithmetic additive test pattern generators [logic test]. ETW 2003: 9-14 - [c4]Josep Rius, Alejandro Peidro, Salvador Manich, Rosa Rodríguez-Sánchez:
Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results. PATMOS 2003: 80-89 - 2002
- [c3]Bram Kruseman, Stefan van den Oetelaar, Josep Rius:
Comparison of IDDQ Testing and Very-Low Voltage Testing. ITC 2002: 964-973
1990 – 1999
- 1999
- [c2]Josep Rius, Joan Figueras:
Exploring the Combination of IDDQ and iDDt Testing: Energy Testing. DATE 1999: 543-548 - 1998
- [j3]Antoni Ferré, Eugeni Isern, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras:
IDDQ testing: state of the art and future trends. Integr. 26(1-2): 167-196 (1998) - 1996
- [j2]Josep Rius, Joan Figueras:
Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments. J. Electron. Test. 9(3): 295-310 (1996) - 1995
- [c1]Josep Rius, Joan Figueras:
Detecting IDDQ defective CMOS circuits by depowering. VTS 1995: 324-329 - 1992
- [j1]Josep Rius, Joan Figueras:
Proportional BIC sensor for current testing. J. Electron. Test. 3(4): 387-396 (1992)
Coauthor Index
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