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2020 – today
- 2024
[c10]Tianxia Xie
, Xinning Liu, Yingjie He:
Association Analysis and Cross-Selling Strategy for Sports Products Based on Apriori and K-means Algorithms. ICCBD 2024: 129-133- [c9]An Guo, Xi Chen, Fangyuan Dong, Jinwu Chen, Zhihang Yuan, Xing Hu, Yuanpeng Zhang, Jingmin Zhang, Yuchen Tang, Zhican Zhang, Gang Chen, Dawei Yang, Zhaoyang Zhang, Lizheng Ren, Tianzhu Xiong, Bo Wang, Bo Liu, Weiwei Shan, Xinning Liu, Hao Cai, Guangyu Sun, Jun Yang, Xin Si:
34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs. ISSCC 2024: 570-572 - 2023
- [j15]Weiwei Shan, Yuqiang Cui, Wentao Dai, Xinning Liu, Jingjing Guo, Peng Cao, Jun Yang:
An efficient path delay variability model for wide-voltage-range digital circuits. Sci. China Inf. Sci. 66(2) (2023) - 2022
- [j14]Hao Cai, Xinfang Tong, Pengcheng Wu, Xinning Liu, Bo Liu:
Bit-error-rate aware sensing-error correction interaction in spintronic MRAM. J. Syst. Archit. 128: 102557 (2022) - [j13]Xinning Liu, Xiaomin Li, Huanqing Zhang, Chenyang Li, Lizheng Ren, Qing Chen, Yibo Xu, Jun Yang:
SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU. IEEE J. Solid State Circuits 57(1): 103-114 (2022) - [j12]Hao Cai, Yanan Guo, Bo Liu, Mingyang Zhou, Juntong Chen, Xinning Liu, Jun Yang:
Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell. IEEE Trans. Circuits Syst. I Regul. Pap. 69(4): 1519-1531 (2022) - 2021
- [c8]Xiaomin Li, Yibo Xu, Lizheng Ren, Weiwei Ge, Jianlong Cai, Xinning Liu, Jun Yang:
29.8 115nA@3V ULPMark-CP Score 1205 SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU. ISSCC 2021: 100-102 - [i1]Hao Cai, Yanan Guo, Bo Liu, Mingyang Zhou, Juntong Chen, Xinning Liu, Jun Yang:
Proposal of Analog In-Memory Computing with Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell. CoRR abs/2110.03937 (2021)
2010 – 2019
- 2019
- [j11]Li Yang, Zhi Qi, Zeheng Liu, Hao Liu, Ming Ling, Longxing Shi, Xinning Liu:
An embedded implementation of CNN-based hand detection and orientation estimation algorithm. Mach. Vis. Appl. 30(6): 1071-1082 (2019) - [j10]Hao Cai, You Wang, Lirida Alves de Barros Naviner, Xinning Liu, Weiwei Shan, Jun Yang, Weisheng Zhao:
Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 239-250 (2019) - [c7]Xinning Liu, Song Jia, Hanzun Zhang:
A Novel High-speed FPGA-based True Random Number Generator Based on Chaotic Ring Oscillator. ASICON 2019: 1-4 - 2018
- [j9]Weiwei Shan, Xinning Liu, Minyi Lu, Liang Wan, Jun Yang:
A Low-Overhead Timing Monitoring Technique for Variation-Tolerant Near-Threshold Digital Integrated Circuits. IEEE Access 6: 138-145 (2018) - [j8]Xinchao Shang, Weiwei Shan, Xinning Liu:
Design and Implementation of a Reconfigurable Cryptographic Coprocessor with Multiple Side-Channel Attacks Countermeasures. J. Circuits Syst. Comput. 27(11): 1850180:1-1850180:20 (2018) - [j7]Jun Yang, Hao Ji, Yichen Guo, Jizhe Zhu, Yuan Zhuang, Zhi Li, Xinning Liu, Longxing Shi:
A Double Sensing Scheme With Selective Bitline Voltage Regulation for Ultralow-Voltage Timing Speculative SRAM. IEEE J. Solid State Circuits 53(8): 2415-2426 (2018) - [j6]Weiwei Shan, Liang Wan, Xinning Liu, Xinchao Shang, Wentao Dai, Shuai Shao, Jun Yang, Longxing Shi:
A Low Overhead, Within-a-Cycle Adaptive Clock Stretching Circuit With Wide Operating Range in 40-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1718-1722 (2018) - [j5]Wentao Dai, Weiwei Shan, Xinchao Shang, Xinning Liu, Hao Cai, Jun Yang:
HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3907-3917 (2018) - [c6]Hao Cai, Menglin Han, You Wang, Lirida A. B. Naviner, Xinning Liu, Jun Yang, Weisheng Zhao:
Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power. DCIS 2018: 1-5 - [c5]Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner, Xinning Liu, Jun Yang, Weisheng Zhao:
MRAM-on-FDSOI Integration: A Bit-Cell Perspective. ISVLSI 2018: 263-268 - 2017
- [j4]Jingjing Guo, Jizhe Zhu, Min Wang, Jianxin Nie, Xinning Liu, Wei Ge, Jun Yang:
Analytical inverter chain's delay and its variation model for sub-threshold circuits. IEICE Electron. Express 14(11): 20170390 (2017) - [j3]Weiwei Shan, Xinning Liu, Minyi Lu, Shuai Shao, Zhikuang Cai, Jun Yang:
An improved timing error prediction monitor for wide adaptive frequency scaling. IEICE Electron. Express 14(21): 20170808 (2017) - [c4]Tailong Xu, Feng Xue, Zhikuang Cai, Xinning Liu, Shuo Meng:
A harmonic-free cell-based all-digital delay-locked loop for die-to-die clock synchronization of 3-D IC. ASICON 2017: 167-170 - [c3]Wentao Dai, Weiwei Shan, Xinning Liu, Jun Yang:
HTD: A light-weight holosymmetrical transition detector based in-situ timing monitoring technique for wide-voltage-range in 40nm CMOS. A-SSCC 2017: 209-212 - [c2]Jingjing Guo, Min Wang, Jizhe Zhu, Xinning Liu, Jun Yang:
Analytical hold timing fixing for sub-threshold circuit based on its lognormal distribution. PATMOS 2017: 1-8 - 2015
- [j2]Xinning Liu, Yuxiang Niu, Jun Yang, Peng Cao:
A GPS Bit Synchronization Method Based on Frequency Compensation. IEICE Trans. Commun. 98-B(4): 746-753 (2015) - 2012
- [j1]Xinning Liu, Chen Mei, Peng Cao, Min Zhu, Longxing Shi:
Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications. IEICE Trans. Inf. Syst. 95-D(2): 374-382 (2012) - [c1]Shuo Shi, Xinning Liu, Xuemai Gu:
An energy-efficiency Optimized LEACH-C for wireless sensor networks. CHINACOM 2012: 487-492
Coauthor Index
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