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ORCIDHugh Mair
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2020 – today
- 2024
[c18]Anshul Varma, Sumanth Gururajarao, HsinChen Chen, Tao Chen, Gordon Gammie, Hugh Mair, Jen-Hang Yang, Hao-Hsiang Yu, Shun-Chieh Chang, Cheng-Hao Yang, Li-An Huang, Kumar Ramanathan, Ramesh Halli, Efron Ho, Ta-Wen Hung, Sung S.-Y. Hsueh, LiangChe Li, Achuta Thippana, Ericbill Wang, Sa Hwang:
2.1 A 4nm 3.4GHz Tri-Gear Fully Out-of-Order ARMv9.2 CPU Subsystem-Based 5G Mobile SoC. ISSCC 2024: 36-38- [c17]Chien-Yu Lu, Bo-Jr Huang, Min-Chieh Chen, Ollie Tsai, Alfred Tsai, Eric Jia-Wei Fang, Yuju Cho, Harry H. Chen, Ping Kao, Ericbill Wang, Hugh Mair, Shih-Arn Hwang:
14.4 A Fully Digital Current Sensor Offering Per-Core Runtime Power for System Budgeting in a 4nm-Plus Octa-Core CPU. ISSCC 2024: 260-262 - 2023
- [c16]Bo-Jr Huang, Alfred Tsai, Lear Hsieh, Kathleen Chang, C.-J. Tsai, Jia-Ming Chen, Eric Jia-Wei Fang, Sung S.-Y. Hsueh, Jack Ciao, Barry Chen, Chuck Chang, Ping Kao, Ericbill Wang, Harry H. Chen, Hugh Mair, Shih-Arn Hwang:
A 5G Mobile Gaming-Centric SoC with High-Performance Thermal Management in 4nm FinFET. ISSCC 2023: 40-41 - 2022
- [c15]Ashish Nayak, HsinChen Chen, Hugh Mair, Rolf Lagerquist, Tao Chen, Anand Rajagopalan, Gordon Gammie, Ramu Madhavaram, Madhur Jagota, C. J. Chung, Jenny Wiedemeier, Bala Meera, Chao-Yang Yeh, Maverick Lin, Curtis Lin, Vincent Lin, Jiun Lin, Y. S. Chen, Barry Chen, Cheng-Yuh Wu, Ryan ChangChien, Ray Tzeng, Kelvin Yang, Achuta Thippana, Ericbill Wang, Shih-Arn Hwang:
A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC. ISSCC 2022: 50-52 - 2021
- [c14]Sanu Mathew, Shidhartha Das, Hugh Mair:
Session 4 Overview: Processors Digital Architectures and Systems Subcommittee. ISSCC 2021: 52-53 - [c13]HsinChen Chen, Rolf Lagerquist, Ashish Nayak, Hugh Mair, Gokulakrishnan Manoharan, Ericbill Wang, Gordon Gammie, Efron Ho, Anand Rajagopalan, Lee-Kee Yong, Ramu Madhavaram, Madhur Jagota, Chi-Jui Chung, Sudhakar Maruthi, Jenny Wiedemeier, Tao Chen, Henry Hsieh, Daniel Dia, Amjad Sikiligiri, Manzur Rahman, Barry Chen, Curtis Lin, Vincent Lin, Elly Chiang, Cheng-Yuh Wu, Po-Yang Hsu, Jason Tsai, Wade Wu, Achuta Thippana, S. A. Huang:
A 7nm 5G Mobile SoC Featuring a 3.0GHz Tri-Gear Application Processor Subsystem. ISSCC 2021: 54-56 - [c12]Hugh Mair, Shinichiro Shiratake, Eric Karl, Thomas Burd, Jonathan Chang, Debbie Marr, Samuel Naffziger, Henk Corporaal, Ken Takeuchi, Naresh R. Shanbhag:
SE1: What Technologies Will Shape the Future of Computing? ISSCC 2021: 537-538 - 2020
- [c11]Hugh Mair, Ericbill Wang, Ashish Nayak, Rolf Lagerquist, Loda Chou, Gordon Gammie, HsinChen Chen, Lee-Kee Yong, Manzur Rahman, Jenny Wiedemeier, Ramu Madhavaram, Alex Chiou, Blundt Li, Vincent Lin, Rory Huang, Michael Yanq, Achuta Thippana, Osric Su, S. A. Huang:
2.5 A 7nm FinFET 2.5GHz/2.0GHz Dual-Gear Octa-Core CPU Subsystem with Power/Performance Enhancements for a Fully Integrated 5G Smartphone SoC. ISSCC 2020: 50-52
2010 – 2019
- 2017
- [c10]Hugh Mair, Ericbill Wang, Alice Wang, Ping Kao, Yuwen Tsai, Sumanth Gururajarao, Rolf Lagerquist, Jin Son, Gordon Gammie, Gordon Lin, Achuta Thippana, Kent Li, Manzur Rahman, Wuan Kuo, David Yen, Yi-Chang Zhuang, Ue Fu, Hung-Wei Wang, Mark Peng, Cheng-Yuh Wu, Taner Dosluoglu
, Anatoly Gelman, Daniel Dia, Girishankar Gurumurthy, Tony Hsieh, W. X. Lin, Ray Tzeng, Jengding Wu, C. H. Wang, Uming Ko:
3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance. ISSCC 2017: 56-57 - 2016
- [c9]Hugh Mair, Gordon Gammie, Alice Wang, Rolf Lagerquist, C. J. Chung, Sumanth Gururajarao, Ping Kao, Anand Rajagopalan, Anirban Saha, Amit Jain, Ericbill Wang, Shichin Ouyang, Huajun Wen, Achuta Thippana, HsinChen Chen, Syed Rahman, Minh Chau, Anshul Varma, Brian Flachs, Mark Peng, Alfred Tsai, Vincent Lin, Ue Fu, Wuan Kuo, Lee-Kee Yong, Clavin Peng, Leo Shieh, Jengding Wu, Uming Ko:
4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance. ISSCC 2016: 76-77 - [c8]Hugh Mair, Atsushi Kawasumi:
Session 17 overview: SRAM. ISSCC 2016: 304-305 - 2015
- [c7]Hugh Mair, Gordon Gammie, Alice Wang, Sumanth Gururajarao, Ichiro Lin, HsinChen Chen, Wuan Kuo, Anand Rajagopalan, Wei-Zheng Ge, Rolf Lagerquist, Syed Rahman, C. J. Chung, Simon Wang, Lee-Kee Wong, Yi-Chang Zhuang, Kent Li, Jidong Wang, Minh Chau, Yijing Liu, Daniel Dia, Mark Peng, Uming Ko:
23.3 A highly integrated smartphone SoC featuring a 2.5GHz octa-core CPU with advanced high-performance and low-power techniques. ISSCC 2015: 1-3 - 2012
- [j3]Nathan Ickes, Gordon Gammie, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko:
A 28 nm 0.6 V Low Power DSP for Mobile Applications. IEEE J. Solid State Circuits 47(1): 35-46 (2012) - 2011
- [c6]Gordon Gammie, Nathan Ickes, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko:
A 28nm 0.6V low-power DSP for mobile applications. ISSCC 2011: 132-134 - [c5]Mahmut E. Sinangil, Hugh Mair, Anantha P. Chandrakasan:
A 28nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6V. ISSCC 2011: 260-262 - [c4]Andrew K. Joy, Hugh Mair, Hae-Chang Lee, Arnold Feldman, Clemenz L. Portmann, Neil Bulman, Eugenia Cordero Crespo, Peter Hearne, Patty Huang, Ben Kerr, Pulkit Khandelwal, Franz Kuhlmann, Shaun Lytollis, Joaquim Machado, Casey Morrison, Scott Morrison, Shahriar Rabii, Dushmantha Rajapaksha, Vishnu Ravinuthula, Giuseppe Surace:
Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2Vpp voltage-mode driver. ISSCC 2011: 350-351 - 2010
- [j2]Gordon Gammie, Alice Wang, Hugh Mair, Rolf Lagerquist, Minh Chau, Philippe Royannez, Sumanth Gururajarao, Uming Ko:
SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors. Proc. IEEE 98(2): 144-159 (2010)
2000 – 2009
- 2008
- [c3]Gordon Gammie, Alice Wang, Minh Chau, Sumanth Gururajarao, Robert Pitts, Fabien Jumel, Stacey Engel, Philippe Royannez, Rolf Lagerquist, Hugh Mair, Jeff Vaccani, Greg Baldwin, Keerthi Heragu, Rituparna Mandal, Michael Clinton, Don Arden, Uming Ko:
A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques. ISSCC 2008: 258-259 - 2007
- [c2]Philippe Royannez, Hugh Mair, Michael Clinton, Uming Ko:
Solutions for logic and processor core design at the 45nm technology node & and below. ICECS 2007: 923-926 - 2005
- [c1]Philippe Royannez, Hugh Mair, Franck Dahan, Mike Wagner, Mark Streeter, Laurent Bouetel, Joel Blasquez, H. Clasen, G. Semino, Julie Dong, D. Scott, B. Pitts, Claudine Raibaut, Uming Ko:
A design platform for 90-nm leakage reduction techniques. DAC 2005: 549-550 - 2000
- [j1]Hugh Mair, Liming Xiu:
An architecture of high-performance frequency and phase synthesis. IEEE J. Solid State Circuits 35(6): 835-846 (2000)
Coauthor Index
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