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ORCIDYuyang Ye 0001
Person information
- unicode name: 叶雨阳
- affiliation: Chinese University of Hong Kong (CUHK), Department of Computer Science and Engineering, Shatin, Hong Kong
Other persons with the same name
- Yuyang Ye — disambiguation page
- Yuyang Ye 0002
![[0000-0002-1513-7814]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-1513-7814")
— Rutgers University, Business School, Newark, NJ, USA
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2020 – today
- 2025
[j7]Shuaibo Huang, Yuyang Ye, Hao Yan, Longxing Shi:
ARS-Flow 2.0: An enhanced design space exploration flow for accelerator-rich system based on active learning. Integr. 101: 102315 (2025)- [j6]Yuyang Ye, Peng Xu, Lizheng Ren, Tinghuan Chen, Hao Yan, Bei Yu, Longxing Shi:
Learning-Driven Physically Aware Large-Scale Circuit Gate Sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(5): 1901-1914 (2025) - [j5]Tianzhu Xiong, Yuyang Ye, Xin Si, Jun Yang:
A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation. IEEE Trans. Very Large Scale Integr. Syst. 33(1): 52-65 (2025) - [c10]Xiangfei Hu, Yuyang Ye, Tinghuan Chen, Hao Yan, Bei Yu:
Timing-Driven Approximate Logic Synthesis Based on Double-Chase Grey Wolf Optimizer. DATE 2025: 1-7 - [c9]Fangzhou Liu, Guannan Guo, Yuyang Ye, Ziyi Wang, Wenjie Fu, Weihua Sheng, Bei Yu:
GraphCAD: Leveraging Graph Neural Networks for Accuracy Prediction Handling Crosstalk-affected Delays. ISPD 2025: 125-133 - 2024
- [j4]Yuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu, Longxing Shi:
Timing-Driven Technology Mapping Approximation Based on Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(9): 2755-2768 (2024) - [j3]Yuyang Ye, Tinghuan Chen, Zicheng Wang, Hao Yan, Bei Yu, Longxing Shi:
Fast and Accurate Aging-Aware Cell Timing Model via Graph Learning. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 156-160 (2024) - [c8]Xu Cheng, Yuyang Ye, Guoqing He, Qianqian Song, Peng Cao:
Heterogeneous Graph Attention Network Based Statistical Timing Library Characterization with Parasitic RC Reduction. ASPDAC 2024: 171-176 - [c7]Guoqing He, Wenjie Ding, Yuyang Ye, Xu Cheng, Qianqian Song, Peng Cao:
An Optimization-aware Pre-Routing Timing Prediction Framework Based on Heterogeneous Graph Learning. ASPDAC 2024: 177-182 - [c6]Shuaibo Huang, Yuyang Ye, Hao Yan, Longxing Shi:
ARS-Flow: A Design Space Exploration Flow for Accelerator-rich System based on Active Learning. ASPDAC 2024: 213-218 - [c5]Yunfan Zuo, Yuyang Ye, Hongchao Zhang, Tinghuan Chen, Hao Yan, Longxing Shi:
A Graph-Learning-Driven Prediction Method for Combined Electromigration and Thermomigration Stress on Multi-Segment Interconnects. DATE 2024: 1-6 - [c4]Peng Xu, Su Zheng, Yuyang Ye, Chen Bai, Siyuan Xu, Hao Geng, Tsung-Yi Ho, Bei Yu:
RankTuner: When Design Tool Parameter Tuning Meets Preference Bayesian Optimization. ICCAD 2024: 122:1-122:7 - [i2]Yuyang Ye, Peng Xu, Lizheng Ren, Tinghuan Chen, Hao Yan, Bei Yu, Longxing Shi:
Learning-driven Physically-aware Large-scale Circuit Gate Sizing. CoRR abs/2403.08193 (2024) - [i1]Xiangfei Hu, Yuyang Ye, Tinghuan Chen, Hao Yan, Bei Yu:
Timing-driven Approximate Logic Synthesis Based on Double-chase Grey Wolf Optimizer. CoRR abs/2411.10990 (2024) - 2023
- [j2]Qian Chen, Yuyang Ye, Meng Li, Hao Yan, Longxing Shi:
Optimized matrix ordering of sparse linear solver using a few-shot model for circuit simulation. Integr. 93: 102062 (2023) - [j1]Yuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu, Longxing Shi:
Aging-Aware Critical Path Selection via Graph Attention Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 5006-5019 (2023) - [c3]Yuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu, Longxing Shi:
Graph-Learning-Driven Path-Based Timing Analysis Results Predictor from Graph-Based Timing Analysis. ASP-DAC 2023: 547-552 - [c2]Yuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu, Longxing Shi:
Fast and Accurate Wire Timing Estimation Based on Graph Learning. DATE 2023: 1-6 - [c1]Yuyang Ye, Zonghui Wang, Zun Xue, Ziqi Wang, Yifei Gao, Hao Yan:
FPGNN-ATPG: An Efficient Fault Parallel Automatic Test Pattern Generator. ACM Great Lakes Symposium on VLSI 2023: 299-304
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