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ORCIDISLPED 1996: Monterey, California, USA
- Mark Horowitz, Jan M. Rabaey, Brock Barton, Massoud Pedram:
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996, Monterey, California, USA, August 12-14, 1996. IEEE 1996, ISBN 0-7803-3571-6 - Dan Dobberpuhl:
The design of a high performance low power microprocessor. 11-16 - K. Bult, Amit Burstein, D. Chang, Michael J. Dong, M. Fielding, E. Kruglick, J. Ho, F. Lin, Tsung-Hsien, William J. Kaiser, H. Marcy, R. Mukai, Phyllis R. Nelson, F. Newburg, Kristofer S. J. Pister
, Gregory J. Pottie, Henry Sanchez, Oscar M. Stafsudd, K. B. Tan, S. Xue, J. Yao:
Low power systems for wireless microsensors. 17-21 - William H. Mangione-Smith, Phil Seong Ghang, Sean Nazareth, Paul Lettieri, Walt Boring, Rajeev Jain:
A low power architecture for wireless multimedia systems: lessons learned from building a power hog. 23-28 - Paul E. Landman:
High-level power estimation. 29-35 - Thomas L. Martin, Daniel P. Siewiorek:
A power metric for mobile systems. 37-42 - Naresh R. Shanbhag:
Lower bounds on power dissipation for DSP algorithms. 43-48 - Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa:
A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes. 49-54 - Nestoras Tzartzanis, William C. Athas:
Energy recovery for the design of high-speed, low-power static RAMs. 55-60 - Hiroki Morimura, Nobutaro Shibata:
A 1-V 1-Mb SRAM for portable equipment. 61-66 - Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee:
A novel methodology for transistor-level power estimation. 67-72 - Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang:
Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques. 73-78 - Taku Uchino, Fumihiro Minami, Masami Murakata, Takashi Mitsuhashi:
Switching activity analysis for sequential circuits using Boolean approximation method. 79-84 - Patrik Larsson, Chris J. Nicol:
Transition reduction in carry-save adder trees. 85-88 - Lars E. Thon, Ghavam G. Shahidi, Werner Rausch, Gerald P. Coleman, Denny D. Tang, Dominic Schepis, Ronald Schulz, Fariborz Assadaraghi:
250-600 Mhz 12b digital filters in 0.8-0.25um Bulk and SOI CMOS technologies. 89-92 - Maitham Shams, Jo C. Ebergen, Mohamed I. Elmasry:
A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element. 93-96 - Uming Ko, Anthony M. Hill, Poras T. Balsara:
Design techniques for high performance, energy efficient control logic. 97-100 - William C. Athas, Weichuan Liu, Lars J. Svensson:
Energy-recovery CMOS for highly pipelined DSP designs. 101-104 - Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò:
Gate-level current waveform simulation of CMOS integrated circuits. 109-112 - Peter H. Schneider, Shankar Krishnamoorthy:
Effects of correlations on accuracy of power analysis - an experimental study. 113-116 - Tohru Ishihara, Hiroto Yasuura:
Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. 117-120 - Srinivas Katkoori, Ranga Vemuri:
Simulation based architectural power estimation for PLA-based controllers. 121-124 - Dirk Rabe, Wolfgang Nebel:
Short circuit power consumption of glitches. 125-128 - Jun Ma, Han-Bin Liang, Michael Kaneshiro, Carl Kyono, Robert Pryor, Ken Papworth, Sunny Cheng:
A graded-channel MOS (GCMOS) VLSI technology for low power DSP applications. 129-132 - L. Richard Carley, David F. Guillou, Suresh Santhanam:
Fabrication and performance of mesa interconnect. 133-137 - Pong-Fei Lu, Jin Ji, Ching-Te Chuang, Lawrence F. Wagner, Chang-Ming Hsieh, Jente Benedict Kuang, L. Hsu, Mario M. Pelella Jr., Shao-Fu Sanford Chu, Carl J. Anderson:
Floating body effects in partially-depleted SOI CMOS circuits. 139-144 - Amitava Chatterjee, Mahalingam Nandakumar, Ih-Chin Chen:
An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits. 145-150 - Luis A. Plana, Steven M. Nowick:
Concurrency-oriented optimization for low-power asynchronous systems. 151-156 - Jui-Ming Chang, Massoud Pedram:
Energy minimization using multiple supply voltages. 157-162 - R. Iris Bahar, M. Burns, Gary D. Hachtel, Enrico Macii, H. Shin, Fabio Somenzi:
Symbolic computation of logic implications for technology-dependent low-power synthesis. 163-168 - Olivier Coudert, Ramsey W. Haddad:
Integrated resynthesis for low power. 169-174 - James Burr, Laszlo Gal, Ramsey W. Haddad, Jan M. Rabaey, Bruce Wooley:
Which has greater potential power impact: high-level design and algorithms or innovative low power technology? (panel). 175 - Koichiro Mashiko:
How to design low-power digital cellular phones. 177-180 - Kurt Keutzer, Olivier Coudert, Ramsey W. Haddad:
What is the state of the art in commercial EDA tools for low power? 181-187 - Labros Bisdounis, Odysseas G. Koufopavlou, Spiridon Nikolaidis:
Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices. 189-192 - Azeez J. Bhavnagarwala, Vivek De, Blanca Austin, James D. Meindl:
Circuit techniques for low-power CMOS GSI. 193-196 - Kai Chen, Yuhua Cheng, Chenming Hu:
Device design for low power electronics with accurate deep submicrometer LDD-MOSFET models. 197-200 - R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili:
Energy delay analysis of partial product reduction methods for parallel multiplier implementation. 201-204 - Alberto Nannarelli, Tomás Lang:
Low-power radix-4 divider. 205-208 - Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens:
Power comparisons for barrel shifters. 209-212 - Hirotsugu Kojima, Avadhani Shridhar:
Interlaced accumulation programming for low power DSP. 213-216 - Manish Goel, Naresh R. Shanbhag:
Low-power adaptive filter architectures via strength reduction. 217-220 - Shivaling S. Mahant-Shetti, Carl Lemonds, Poras T. Balsara:
Leap frog multiplier. 221-223 - Andrzej J. Strojwas, Michele Quarantelli, J. Borel, Carlo Guardiani, Germano Nicollini, G. Crisenza, Bruno Franzini, J. Wiart:
Manufacturability of low power CMOS technology solutions. 225-232 - Xinghai Tang, Vivek De, James D. Meindl:
Effects of random MOSFET parameter fluctuations on total power consumption. 233-236 - M. Eisele, Jörg Berthold, Doris Schmitt-Landsiedel, R. Mahnkopf:
The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. 237-242 - Douglas Mercer, Larry Singer:
12-b 125 MSPS CMOS D/A designed for spectral performance. 243-246 - L. Grisoni, Alexandre Heubi, Peter Balsiger, Fausto Pellandini:
Implementation of a micro power 15-bit "floating-point" A/D converter. 247-252 - Alexandre Heubi, Peter Balsiger, Fausto Pellandini:
Micro power "relative precision" 13 bits cyclic RSD A/D converter. 253-257 - Marios C. Papaefthymiou, Kumar N. Lalgudi:
Fixed-phase retiming for low power design. 259-264 - Patrick Vuillod, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli:
Clock skew optimization for peak current reduction. 265-270 - Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung:
Simultaneous buffer and wire sizing for performance and power optimization. 271-276 - Domine Leenaerts, G. H. M. Joordens, Johannes A. Hegt:
A low power high performance switched-current multiplier. 277-280 - Rafael Fried, Ziv Azmanov:
Low-power frequency multiplier with one cycle lock-in time and 100ppm frequency resolution, for system power-management. 281-284 - Fan You, Sherif H. K. Embabi, Edgar Sánchez-Sinencio:
A 1.5V class AB output buffer. 285-288 - Preeti Ranjan Panda, Nikil D. Dutt:
Low-power mapping of behavioral arrays to multiple memories. 289-292 - Christopher K. Lennard, Premal Buch, A. Richard Newton:
Logic synthesis using power-sensitive don't care sets. 293-296 - Dhiraj K. Pradhan, Mitrajit Chatterjee, Madhu V. Swarna, Wolfgang Kunz:
Gate-level synthesis for low-power using new transformations. 297-300 - Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi:
Controller re-specification to minimize switching activity in controller/data path circuits. 301-304 - Qiuting Huang, Philipp Basedau:
A 200 µA, 78 MHz CMOS crystal-oscillator digitally trimmable to 0.3 ppm. 305-308 - Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Toshiaki Mori, Kenji Matsuo, Masakazu Kakumu, Takayasu Sakurai:
Substrate noise influence on circuit performance in variable threshold-voltage scheme. 309-312 - Gu-Yeon Wei, Mark Horowitz:
A low power switching power supply for self-clocked systems. 313-317 - Godi Fischer, James C. Daly, Chun Yang, Conrad W. Recksiek, Kevin D. Friedland:
Design of a programmable temperature monitoring device for tagging small fish. 319-322 - Akhilesh Tyagi:
Entropic bounds on FSM switching. 323-328 - Mahadevamurty Nemani, Farid N. Najm:
High-level power estimation and the area complexity of Boolean functions. 329-334 - Mircea R. Stan, Wayne P. Burleson:
Two dimensional codes for low power. 335-340 - Rafael Llopis, Manoj Sachdev:
Low power, testable dual edge triggered flip-flops. 341-345 - Anantha P. Chandrakasan, Vadim Gutnik, Thucydides Xanthopoulos:
Data driven signal processing: an approach for energy efficient computing. 347-352 - Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki:
Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer. 353-358 - Sven Wuytack, Francky Catthoor, Lode Nachtergaele, Hugo De Man:
Power exploration for data dominated video applications. 359-364 - Kerry Bernstein, John E. Bertsch, William F. Clark, John J. Ellis-Monaghan, Larry G. Heller, Edward J. Nowak:
Practical performance/power alternatives within an existing CMOS technology generation. 365-370 - Vivek De, James D. Meindl:
A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI). 371-375 - David J. Frank:
Comparison of high speed voltage-scaled conventional and adiabatic circuits. 377-380 - Ram K. Krishnamurthy, Ihor Lys, L. Richard Carley:
Static power driven voltage scaling and delay driven buffer sizing in mixed swing QuadRail for sub-1V I/O swings. 381-386
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