default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDICCAD 2002: San Jose, California, USA
- Lawrence T. Pileggi, Andreas Kuehlmann:
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002. ACM / IEEE Computer Society 2002, ISBN 0-7803-7607-2 - Hongmei Li, Jorge Carballido, Harry H. Yu, Vladimir I. Okhmatovski
, Elyse Rosenbaum, Andreas C. Cangellaris:
Comprehensive frequency-dependent substrate noise analysis using boundary element methods. 2-9 - Eelco Schrik, Patrick M. Dewilde, N. P. van der Meijs:
Theoretical and practical validation of combined BEM/FEM substrate resistance modeling. 10-15 - Dipak Sitaram, Yu Zheng, Kenneth L. Shepard:
Implicit treatment of substrate and power-ground losses in return-limited inductance extraction. 16-22 - Takayasu Sakurai:
Minimizing power across multiple technology and design levels. 24-27 - Tadahiro Kuroda:
Optimization and control of VDD and VTH for low-power, high-speed CMOS design. 28-34 - Robert W. Brodersen, Mark Horowitz, Dejan Markovic, Borivoje Nikolic, Vladimir Stojanovic:
Methods for true power minimization. 35-42 - Shih-Ping Lin, Yao-Wen Chang:
A novel framework for multilevel routing considering routability and performance. 44-50 - Jason Cong, Min Xie, Yan Zhang:
An enhanced multilevel routing system. 51-58 - Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou:
Track assignment: a desirable intermediate step between global routing and detailed routing. 59-66 - Hua Xiang, Kai-Yuan Chao, D. F. Wong:
ECO algorithms for removing overlaps between power rails and signal wires. 67-74 - Nahmsuk Oh, Rohit Kapur, Thomas W. Williams:
Fast seed computation for reseeding shift register in test pattern compression. 76-81 - Irith Pomeranz, Sudhakar M. Reddy:
On undetectable faults in partial scan circuits. 82-86 - Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski:
Conflict driven techniques for improving deterministic test pattern generation. 87-93 - Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng:
On theoretical and practical considerations of path selection for delay fault testing. 94-100 - Satnam Singh:
Interface specification for reconfigurable components. 102-109 - Lin Zhong, Niraj K. Jha:
Interconnect-aware high-level synthesis for low power. 110-117 - Ankur Srivastava, Majid Sarrafzadeh:
Predictability: definition, ananlysis and optimization. 118-121 - Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley:
Simplifying Boolean constraint solving for random simulation-vector generation. 123-127 - Katarzyna Radecka, Zeljko Zilic:
Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. 128-131 - Roberto Passerone, Luca de Alfaro, Thomas A. Henzinger, Alberto L. Sangiovanni-Vincentelli:
Convertibility verification and converter synthesis: two faces of the same coin. 132-139 - James T. Kao, Siva G. Narendra, Anantha P. Chandrakasan:
Subthreshold leakage modeling and reduction techniques. 141-148 - Jianwen Zhu:
Symbolic pointer analysis. 150-157 - Priya Unnikrishnan, Guangyu Chen, Mahmut T. Kandemir, D. R. Mudgett:
Dynamic compilation for energy adaptation. 158-163 - Greg Stitt, Frank Vahid:
Hardware/software partitioning of software binaries. 164-170 - Tim (Tianming) Kong:
A novel net weighting algorithm for timing-driven placement. 172-176 - Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh:
Timing-driven placement using design hierarchy guided constraint generation. 177-180 - Cristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis:
Multi-objective circuit partitioning for cutsize and path-based delay minimization. 181-185 - Paul S. Zuchowski, Christopher B. Reynolds, Richard J. Grupp, Shelly G. Davis, Brendan Cremen, Bill Troxel:
A hybrid ASIC and FPGA architecture. 187-194 - David E. Lackey, Paul S. Zuchowski, Thomas R. Bednar, Douglas W. Stout, Scott W. Gould, John M. Cohn:
Managing power and performance for System-on-Chip designs using Voltage Islands. 195-202 - Tanay Karnik, Shekhar Borkar, Vivek De:
Sub-90nm technologies: challenges and opportunities for CAD. 203-206 - Andrea Pacelli:
A local circuit topology for inductive parasitics. 208-214 - Tsung-Hao Chen, Clement Luk, Hyungsuk Kim, Charlie Chung-Ping Chen:
INDUCTWISE: inductance-wise interconnect simulator and extractor. 215-220 - Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar:
A precorrected-FFT method for simulating on-chip inductance. 221-227 - Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen:
On the difference between two widely publicized methods for analyzing oscillator phase behavior. 229-233 - Kenneth Francken, Martin Vogels, Ewout Martens, Georges G. E. Gielen:
A behavioral simulation tool for continuous-time delta sigma modulators. 234-239 - Jaijeet S. Roychowdhury:
Making Fourier-envelope simulation robust. 240-245 - Soha Hassoun, Charles J. Alpert, Meera Thiagarajan:
Optimal buffered routing path constructions for single and multiple clock domain systems. 247-253 - Muzhou Shao, D. F. Wong, Youxin Gao, Li-Pen Yuan, Huijing Cao:
Shaping interconnect for uniform current density. 254-259 - Andrew B. Kahng, Bao Liu, Ion I. Mandoiu:
Non-tree routing for reliability and yield improvement. 260-266 - Pasquale Cocchini:
Concurrent flip-flop and repeater insertion for high performance integrated circuits. 268-273 - Tao Lin, Lawrence T. Pileggi:
Throughput-driven IC communication fabric synthesis. 274-279 - Harshit K. Shah, Pun H. Shiu, Brian Bell, Mamie Aldredge, Namarata Sopory, Jeff Davis:
Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects. 280-284 - Sanjay Ramnath, Frederic Neuveux, Mokhtar Hirech, Felix Ng:
Test-model based hierarchical DFT synthesis. 286-293 - Xiaoding Chen, Michael S. Hsiao:
Characteristic faults and spectral information for logic BIST. 294-298 - Ozgur Sinanoglu, Alex Orailoglu:
A novel scan architecture for power-efficient, rapid test. 299-303 - Peter J. Vancorenland, Philippe Coppejans, Wouter De Cock, Paul Leroux, Michiel Steyaert:
Optimization of a fully integrated low power CMOS GPS receiver. 305-308 - Adil Koukab, Kaustav Banerjee, Michel J. Declercq:
Analysis and optimization of substrate noise coupling in single-chip RF transceiver design. 309-316 - Maria del Mar Hershenson:
Design of pipeline analog-to-digital converters via geometric programming. 317-324 - Luca Daniel, Alberto L. Sangiovanni-Vincentelli, Jacob K. White:
Proximity templates for modeling of skin and proximity effects on packages and high frequency interconnect. 326-333 - Rafael Escovar, Roberto Suaya:
Transmission line design of clock trees. 334-340 - Guoan Zhong, Cheng-Kok Koh, Kaushik Roy:
On-chip interconnect modeling by wire duplication. 341-346 - Matthew M. Ziegler, Mircea R. Stan:
A Case for CMOS/nano co-design. 348-352 - Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes:
Reversible logic circuit synthesis. 353-360 - Bikram Baidya, Tamal Mukherjee:
Extraction and LVS for mixed-domain integrated MEMS layouts. 361-366 - Qi Jing, Tamal Mukherjee, Gary K. Fedder:
Schematic-based lumped parameterized behavioral modeling for suspended MEMS. 367-373 - Mahesh Ketkar, Sachin S. Sapatnekar:
Standby power optimization via transistor sizing and dual threshold voltage assignment. 375-378 - Anoop Iyer, Diana Marculescu:
Power efficiency of voltage scaling in multiple clock, multiple voltage cores. 379-386 - Miodrag Vujkovic, Carl Sechen:
Optimized power-delay curve generation for standard cell ICs. 387-394 - Hiran Tennakoon, Carl Sechen:
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step. 395-402 - Xun Liu, Marios C. Papaefthymiou:
A Markov chain sequence generator for power macromodeling. 404-411 - Lipeng Cao:
Circuit power estimation using pattern recognition techniques. 412-417 - Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw:
Estimation of signal arrival times in the presence of delay noise. 418-422 - Mark A. Lavin, Lars Liebmann:
CAD computation for manufacturability: can we save VLSI technology from itself? 424-431 - Michael Butts, André DeHon, Seth Copen Goldstein:
Molecular electronics: devices, systems and tools for gigagate, gigabit chips. 433-440 - Lintao Zhang, Sharad Malik:
Conflict driven learning in a quantified Boolean Satisfiability solver. 442-449 - Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah:
Generic ILP versus specialized 0-1 ILP: an update. 450-457 - Farzan Fallah:
Binary time-frame expansion. 458-464 - Shihhsien S. Kuo, Michael D. Altman, Jaydeep P. Bardhan, Bruce Tidor, Jacob K. White:
Fast methods for simulation of biomolecule electrostatics. 466-473 - Gang Li, Narayan R. Aluru:
Efficient mixed-domain analysis of electrostatic MEMS. 474-477 - Yehia Massoud, Jacob White:
FastMag: a 3-D magnetostatic inductance extraction program for structures with permeable materials. 478-484 - Andreas C. Lemke, Lars Hedrich, Erich Barke:
Analog circuit sizing based on formal methods using affine arithmetic. 486-489 - Giorgio Biagetti, Simone Orcioni, L. Signoracci, Claudio Turchetti, Paolo Crippa, Michele Alessandrini:
SiSMA: a statistical simulator for mismatch analysis of MOS ICs. 490-496 - Florin Balasa, Sarat C. Maruvada, Karthik Krishnamoorthy:
Efficient solution space exploration based on segment trees in analog placement with symmetry constraints. 497-502 - Jinjun Xiong, Jun Chen, James D. Z. Ma, Lei He:
Post global routing RLC crosstalk budgeting. 504-509 - Rouying Zhan, Haigang Feng, Qiong Wu, Guang Chen, Xiaokang Guan, Albert Z. Wang:
A technology-independent CAD tool for ESD protection device extraction: ESDExtractor. 510-513 - Ruiqi Tian, Ronggang Yu, Xiaoping Tang, D. F. Wong:
On mask layout partitioning for electron projection lithography. 514-518 - Sasha Novakovsky, Shy Shyman, Ziyad Hanna:
High capacity and automatic functional extraction tool for industrial VLSI circuit designs. 520-525 - Hee-Hwan Kwak, In-Ho Moon, James H. Kukula, Thomas R. Shiple:
Combinational equivalence checking through function transformation. 526-533 - Jin Yang, Amit Goel:
GSTE through a case study. 534-541 - Fan Mo, Robert K. Brayton:
Whirlpool PLAs: a regular logic structure and their synthesis. 543-550 - Prabhakar Kudva, Andrew Sullivan, William E. Dougherty:
Metrics for structural logic synthesis. 551-556 - Alan Mishchenko, Robert K. Brayton:
Simplification of non-deterministic multi-valued networks. 557-562 - Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
High-level synthesis of distributed logic-memory architectures. 564-571 - Preeti Ranjan Panda, Lakshmikantam Chitturi:
An energy-conscious algorithm for memory port allocation. 572-576 - Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas J. W. Clarke:
Energy efficient address assignment through minimized memory row switching. 577-581 - Pinhong Chen, Yuji Kukimoto, Kurt Keutzer:
Refining switching window by time slots for crosstalk noise calculation. 583-586 - Vladimir Zolotov, David T. Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy:
Noise propagation and failure criteria for VLSI designs. 587-594 - Li Ding, David T. Blaauw, Pinaki Mazumder:
Efficient crosstalk noise modeling using aggressor and tree reductions. 595-600 - María C. Molina, José M. Mendías, Román Hermida:
Bit-level scheduling of heterogeneous behavioural specifications. 602-608 - Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim:
Coupling-aware high-level interconnect synthesis for low power. 609-613 - Junhyung Um, Jae-Hoon Kim, Taewhan Kim:
Layout-driven resource sharing in high-level synthesis. 614-618 - Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert:
A delay metric for RC circuits based on the Weibull distribution. 620-624 - Larry McMurchie, Carl Sechen:
WTA: waveform-based timing analysis for deep submicron circuits. 625-631 - Jindrich Zejda, Paul Frain:
General framework for removal of clock network pessimism. 632-639 - Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Synthesis of custom processors based on extensible platforms. 641-648 - Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt:
Efficient instruction encoding for automatic instruction set design of configurable ASIPs. 649-654 - Susan Cotterell, Frank Vahid:
Synthesis of customized loop caches for core-based embedded systems. 655-662 - Xinping Zhu, Sharad Malik:
A hierarchical modeling framework for on-chip communication architectures. 663-671 - Jason Cong, Joey Y. Lin, Wangning Long:
A new enhanced SPFD rewiring algorithm. 672-678 - Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton:
Topologically constrained logic synthesis. 679-686 - Victor N. Kravets, Karem A. Sakallah:
Resynthesis of multi-level circuits under tight constraints using symbolic optimization. 687-693 - Shinji Kimura, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara:
Folding of logic functions and its application to look up table compaction. 694-697 - Sorin Manolache, Petru Eles, Zebo Peng:
Schedulability analysis of multiprocessor real-time applications with stochastic task execution times. 699-706 - Peng Rong, Massoud Pedram:
Battery-aware power management based on Markovian decision processes. 707-713 - Weiping Liao, Joseph M. Basile, Lei He:
Leakage power modeling and reduction with data retention. 714-719 - Steven M. Martin, Krisztián Flautner, Trevor N. Mudge, David T. Blaauw:
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. 721-725 - Bren Mochocki, Xiaobo Sharon Hu, Gang Quan:
A realistic variable voltage scheduling model for real-time applications. 726-731 - Kihwan Choi, Karthik Dantu, Wei-Chung Cheng, Massoud Pedram:
Frame-based dynamic voltage and frequency scaling for a MPEG decoder. 732-737 - Bo Hu, Malgorzata Marek-Sadowska:
Congestion minimization during placement without estimation. 739-745 - Charles J. Alpert, Gi-Joon Nam, Paul Villarrubia:
Free space management for cut-based placement. 746-751 - Deshanand P. Singh, Stephen Dean Brown:
Incremental placement for layout driven optimizations on FPGAs. 752-759 - Hui Zheng, Lawrence T. Pileggi:
Robust and passive model order reduction for circuits containing susceptance elements. 761-766 - Yehea I. Ismail:
Efficient model order reduction via multi-node moment matching. 767-774 - Carlos P. Coelho, Joel R. Phillips, Luís Miguel Silveira:
Optimization based passive constrained fitting. 775-780 - Armin Biere, Wolfgang Kunz:
SAT and ATPG: Boolean engines for formal hardware verification. 782-785 - Chih-Wei Jim Chang, Malgorzata Marek-Sadowska:
ATPG-based logic synthesis: an overview. 786-789 - Reinaldo A. Bergamaschi, John M. Cohn:
The A to Z of SoCs. 790-798
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-13 23:58 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
