default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID33rd DCIS 2018: Lyon, France
- Conference on Design of Circuits and Integrated Systems, DCIS 2018, Lyon, France, November 14-16, 2018. IEEE 2018, ISBN 978-1-7281-0171-2
- Gennaro Severino Rodrigues, Ádria Barros de Oliveira, Alberto Bosio, Fernanda Lima Kastensmidt, Edison Pignaton de Freitas
:
ARFT: An Approximative Redundant Technique for Fault Tolerance. 1-6 - Yaiza Montes-Cebrián, Albert Álvarez-Carulla, Jordi Colomer-Farrarons, Manel Puig-Vidal, Jaime López-Sánchez, Pere Lluís Miribel-Català:
A Fuel Cell-based adaptable Self-Powered Event Detection platform enhanced for biosampling applications. 1-6 - Álvaro Hernández, Jesús Ureña, Jose M. Villadangos, Khaoula Mannay:
SoC Architecture for an Ultrasonic Receiver applied to Local Positioning Systems. 1-5 - Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal:
RRAM Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations. 1-6 - Mohan Julien, Serge Bernard, Fabien Soulier, Vincent Kerzerho, Guy Cathébras:
Improvement of Active-Input Current Mirrors Using Adaptive Biasing Technique. 1-4 - David Pescha, Martin Horauer:
Event Storms in IEC 61499 Applications. 1-5 - Erica Tena-Sánchez, Ignacio M. Delgado-Lozano, Juan Núñez, Antonio J. Acosta:
Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits. 1-6 - Samuel Rigault, Nicolas Moeneclaey, Lioua Labrak, Ian O'Connor:
CMOS VCSEL driver dedicated for sub-nanosecond laser pulses generation in SPAD-based time-of-flight rangefinder. 1-6 - Sergi Abadal, Eduard Alarcón:
Data Conversion in Area-Constrained Applications: the Wireless Network-on-Chip Case. 1-6 - Albert Álvarez-Carulla, Yaiza Montes-Cebrián, Manel Puig-Vidal, Jaime López-Sánchez, Jordi Colomer-Farrarons, Pere Lluís Miribel-Català:
Energy-Aware Adaptative Supercapacitor Storage System for Multi-Harvesting Solutions. 1-6 - Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Carmen Baena Oliva, Pilar Parra Fernández, Manuel Valencia-Barrero:
Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher. 1-6 - Jose Angel Miranda Calero, Rodrigo Marino, José Manuel Lanza-Gutiérrez, Teresa Riesgo, Mario García-Valderas, Celia López-Ongil:
Embedded Emotion Recognition within Cyber-Physical Systems using Physiological Signals. 1-6 - Valentin Gutierrez, Gildas Léger:
Single Event Transient injection in large mixed-signal circuits. 1-6 - Ranganathan Hariharan, Tara Ghasempouri, Behrad Niazmand, Jaan Raik:
From RTL Liveness Assertions to Cost-Effective Hardware Checkers. 1-6 - Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose:
Approximate Wireless Networks-on-Chip. 1-6 - Marta Portela-García, V. M. Medina, S. Paton:
Vector-Based Mismatch Shaping circuit for a low IF Multibit Σ∆ ADC. 1-6 - Oussama Elissati, Assia El-Hadbi, Abdelkarim Cherkaoui, Sébastien Rieubon, Laurent Fesquet:
Low Phase-Noise CMOS Quadrature Oscillator based on (N × 4)-stage Self-Timed Ring. 1-5 - Marta Pedro, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Xavier Aymerich:
Investigation of Conductivity Changes in Memristors under Massive Pulsed Characterization. 1-4 - Mounia Kharbouche-Harrari, Rana Alhalabi, Jérémy Postel-Pellerin, Romain Wacquez, Driss Aboulkassimi, Etienne Nowak, Ioan Lucian Prejbeanu, Guillaume Prenat, Gregory di Pendina:
MRAM: from STT to SOT, for security and memory. 1-6 - Amina Annagrebah, E. Bechetoille, H. Chanal, H. Mathez, I. B. Laktineh:
Time-To-Digital Converter with adjustable resolution using a digital Vernier Ring Oscillator. 1-4 - Batya Karp, Mael Gay, Osnat Keren, Ilia Polian:
Security-oriented Code-based Architectures for Mitigating Fault Attacks. 1-6 - Thais Luana Vidal de Negreiros da Silva, Guo-Neng Lu, Patrick Pittet:
Breakdown Voltage Shift of CMOS Buried Quad Junction (BQJ) Detector. 1-6 - Esteve Amat, Alberto del Moral, Joan R. Bausells, Francesc Pérez-Murano, Fabian J. Klüpfel:
Quantum dot location relevance into SET-FET circuits based on FinFET devices. 1-5 - Mahdi Tala, Oliver Schrape, Milos Krstic, Davide Bertozzi:
Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip. 1-6 - Daniel Fortun, Carlos Garcia de la Cueva, Jesús Grajal, Marisa López-Vallejo, Carlos A. López-Barrio:
Performance-oriented Implementation of Hilbert Filters on FPGAs. 1-6 - Iban Barrutia, Amparo Herrera, Benoit Haentjens, Laura Diego, Charles A. Mjema:
Multioctave Distributed MMIC Power Amplifier in Gallium Nitride Technology with P1dB > 31dBm. 1-6 - Mikel Rodriguez, Armando Astarloa, Jesús Lázaro, Unai Bidarte, Jaime Jimenez:
System-on-Programmable-Chip AES-GCM implementation for wire-speed cryptography for SAS. 1-6 - Rui Moutinho Teixeira, José Machado da Silva:
Design for Calibratability of a N-Integer Low-Frequency Phase-Locked Loop. 1-6 - Rui Zhang, Kexin Yang, Taizhi Liu, Linda Milor:
Estimation of the Optimal Accelerated Test Region for FinFET SRAMs Degraded by Front-End and Back-End Wearout Mechanisms. 1-6 - Jiating Luo, Van-Dung Pham, Cédric Killian, Daniel Chillet, Ian O'Connor, Olivier Sentieys, Sébastien Le Beux:
Run-Time management of energy-performance trade-off in Optical Network-on-Chip. 1-6 - Rodrigo B. Capeleiro, Marcelino B. Santos:
Low noise, high efficiency, segmented LCD drivers for ultra-low power applications in 22 nm FD-SOI. 1-6 - Hélène Tap, Laurent Gatet, Emmanuel Moutaye, Blaise Mulliez:
Embedded System for Distance Measurement and Surface Discrimination Applications. 1-6 - Rubén Nieto, Raúl Mateos, Álvaro Hernández:
Finite Precision Analysis of FPGA-based Architecture for FBMC Transmultiplexers in Broadband PLC. 1-6 - Kexin Yang, Rui Zhang, Taizhi Liu, Dae Hyun Kim, Linda Milor:
Optimal Accelerated Test Regions for Time- Dependent Dielectric Breakdown Lifetime Parameters Estimation in FinFET Technology. 1-6 - Rodrigo B. Capeleiro, José M. Leitão, Ricardo Chaves, Marcelino B. Santos:
Low-power frequency monitoring circuit for clock failure detection. 1-6 - Enrico Fraccaroli, Davide Quaglia, Franco Fummi:
Efficient Simulation of Faults in Networked Cyber-Physical Systems. 1-6 - Hao Cai, Menglin Han, You Wang, Lirida A. B. Naviner, Xinning Liu, Jun Yang, Weisheng Zhao:
Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power. 1-5 - Arnaud Toni, Hassan Ihs, Taner Dosluoglu, Remy Cellier, Nacer Abouchi:
An integrated 10MHz 3 States Buck converter for fast transient response in 180nm CMOS. 1-4 - Davide Piumatti, Matteo Sonza Reorda:
Assessing Test Procedure Effectiveness for Power Devices. 1-6 - Iván Zamora, Eyglis Ledesma, Arantxa Uranga, Núria Barniol:
Design of a Fully Integrated CMOS-PMUT System. 1-5 - X. Zuriarrain, Andoni Beriain, Guillermo Bistué, David del Rio, Roc Berenguer, Héctor Solar, Javier Sosa, Juan A. Montiel-Nelson:
A CMOS Low Frequency Analog RFID Front-End for the IoT. 1-6 - Sri Harsha Gade, Sidhartha Sankar Rout, Ravi Kashyap, Sujay Deb:
Reliability Analysis of On-Chip Wireless Links for Many Core WNoCs. 1-6 - Arthur Perodou, Anton Korniienko, Gérard Scorletti, Ian O'Connor:
Systematic Design Method of Passive Ladder Filters using a Generalised Variable. 1-6
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-11 21:36 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
