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ORCIDCODES+ISSS 2008: Atlanta, GA, USA
- Catherine H. Gebotys, Grant Martin:
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008. ACM 2008, ISBN 978-1-60558-470-6
Analysis of parallel application and architecture synthesis
- Haris Javaid, Sri Parameswaran
:
Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study. 1-6 - Giovanni Beltrame, Luca Fossati, Donatella Sciuto:
Concurrency emulation and analysis of parallel applications for multi-processor system-on-chip co-design. 7-12
Flash memory management
- Chin-Hsien Wu:
A time-predictable system initialization design for huge-capacity flash-memory storage systems. 13-18 - Siddharth Choudhuri, Tony Givargis:
Deterministic service guarantees for nand flash using partial block cleaning. 19-24
Application specific processor systems
- Jongeun Lee, Aviral Shrivastava:
Static analysis of processor stall cycle aggregation. 25-30 - Kwangyoon Lee, Alex Orailoglu:
Application specific non-volatile primary memory for embedded systems. 31-36 - Vivy Suhendra, Abhik Roychoudhury, Tulika Mitra:
Scratchpad allocation for concurrent embedded software. 37-42 - Eric Cheung, Harry Hsieh, Felice Balarin:
Software optimization for MPSoC: a mpeg-2 decoder case study. 43-48
Performance enhancement-new techniques for FPGAs and partitioning
- Lance Saldanha, Roman L. Lysecky:
Hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits. 49-54 - Laura Frigerio, Fabio Salice:
A performance-oriented hardware/software partitioning for datapath applications. 55-60 - Greg Stitt, Gaurav Chaudhari, James Coole:
Traversal caches: a first step towards FPGA acceleration of pointer-based data structures. 61-66 - Yvan Eustache, Jean-Philippe Diguet:
Specification and OS-based implementation of self-adaptive, hardware/software embedded systems. 67-72
Multiprocessor and MPSoC architectures
- Chenjie Yu, Peter Petrov:
Distributed and low-power synchronization architecture for embedded multiprocessors. 73-78 - Krutartha Patel, Sri Parameswaran:
LOCS: a low overhead profiler-driven design flow for security of MPSoCs. 79-84 - Jianguo Yao, Xue Liu, Mingxuan Yuan, Zonghua Gu:
Online adaptive utilization control for real-time embedded multiprocessor systems. 85-90 - Frank E. B. Ophelders, Samarjit Chakraborty, Henk Corporaal:
Intra- and inter-processor hybrid performance modeling for MPSoC architectures. 91-96
Exploration, profiling and tuning of embedded systems
- Chen Huang, David Sheldon, Frank Vahid:
Dynamic tuning of configurable architectures: the AWW online algorithm. 97-102 - Yun Liang, Tulika Mitra:
Static analysis for fast and accurate design space exploration of caches. 103-108 - Christos Strydis, Georgi Gaydadjiev:
Profiling of lossless-compression algorithms for a novel biomedical-implant architecture. 109-114 - Mwaffaq Otoom, JoAnn M. Paul:
Holistic design and caching in mobile computing. 115-120
Special Session 1
- Miron Abramovici, Kees Goossens, Bart Vermeulen, Jack Greenbaum, Neal Stollon, Adam Donlin:
You can catch more bugs with transaction level honey. 121-124
Simulation and verification of embedded systems
- J. P. Grossman, Cliff Young, Joseph A. Bank, Kenneth M. Mackenzie, Doug Ierardi, John K. Salmon, Ron O. Dror, David E. Shaw:
Simulation and embedded software development for Anton, a parallel machine with heterogeneous multicore ASICs. 125-130 - Paula Herber, Joachim Fellmuth, Sabine Glesner:
Model checking SystemC designs using timed automata. 131-136 - Heon-Mo Koo, Prabhat Mishra:
Specification-based compaction of directed tests for functional validation of pipelined processors. 137-142 - Matthias Krause, Dominik Englert, Oliver Bringmann, Wolfgang Rosenstiel:
Combination of instruction set simulation and abstract RTOS model execution for fast and accurate target software evaluation. 143-148
Case studies and industrial practices
- Yun Liang, Lei Ju, Samarjit Chakraborty, Tulika Mitra, Abhik Roychoudhury:
Cache-aware optimization of BAN applications. 149-154 - David Sheldon, Frank Vahid:
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs. 155-160 - Simon Schliecker, Mircea Negrean, Gabriela Nicolescu, Pierre G. Paulin, Rolf Ernst:
Reliable performance analysis of a multicore multithreaded system-on-chip. 161-166 - Konstantinos Aisopos, Chien-Chun Chou, Li-Shiuan Peh:
Extending open core protocol to support system-level cache coherence. 167-172
Models and techniques for performance estimation and solution space representation, and a special citation analysis
- Lei Ju, Bach Khoa Huynh, Abhik Roychoudhury, Samarjit Chakraborty:
Performance debugging of Esterel specifications. 173-178 - Hamid Shojaei, Twan Basten, Marc Geilen, Phillip Stanley-Marbell:
SPaC: a symbolic pareto calculator. 179-184 - Simon Schliecker, Jonas Rox, Matthias Ivers, Rolf Ernst:
Providing accurate event models for the analysis of heterogeneous multiprocessor systems. 185-190 - Frank Vahid, Tony Givargis:
Highly-cited ideas in system codesign and synthesis. 191-196
Advanced NoC design techniques
- Leandro Fiorin, Gianluca Palermo, Cristina Silvano:
A security monitoring service for NoCs. 197-202 - Huaxi Gu, Jiang Xu, Zheng Wang:
ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip. 203-208 - Simon Ogg, Bashir M. Al-Hashimi, Alexandre Yakovlev:
Asynchronous transient resilient links for NoC. 209-214 - Nicola Concer, Michele Petracca, Luca P. Carloni:
Distributed flit-buffer flow control for networks-on-chip. 215-220
Keynote address
- Dan J. Gale:
Co-design in the wilderness. 221-222
Special session II
- Xiaobo Sharon Hu, Alexander Khitun, Konstantin K. Likharev, Michael T. Niemier, Mingqiang Bao, Kang L. Wang:
Design and defect tolerance beyond CMOS. 223-230
System level design: throughput, dependability, coherence, and yield
- Girish Venkataramani, Seth Copen Goldstein:
Slack analysis in the system design loop. 231-236 - Felix Reimann, Michael Glaß, Martin Lukasiewycz, Joachim Keinert, Christian Haubelt, Jürgen Teich:
Symbolic voter placement for dependability-aware system synthesis. 237-242 - Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon:
Speculative DMA for architecturally visible storage in instruction set extensions. 243-248 - Love Singhal, Sejong Oh, Eli Bozorgzadeh:
Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors. 249-254
System level power modeling and optimization
- Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt:
Methodology for multi-granularity embedded processor power model generation for an ESL design flow. 255-260 - Michael A. Baker, Viswesh Parameswaran, Karam S. Chatha, Baoxin Li:
Power reduction via macroblock prioritization for power aware H.264 video applications. 261-266 - Gang Quan, Yan Zhang, William Wiles, Pei Pei:
Guaranteed scheduling for repetitive hard real-time tasks under the maximal temperature constraint. 267-272 - Siddharth Garg, Diana Marculescu:
System-level mitigation of WID leakage power variability using body-bias islands. 273-278
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