"A 52-Gb/s Sub-1-pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power ..."

Can Wang et al. (2021)

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DOI: 10.1109/OJCAS.2020.3034819

access: open

type: Journal Article

metadata version: 2023-09-29

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Can Wang, Li Wang, Zhao Zhang, Milad Kalantari Mahmoudabadi, Weimin Shi, C. Patrick Yue:
A 52-Gb/s Sub-1-pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects. IEEE Open J. Circuits Syst. 2: 46-55 (2021)

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