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BibTeX record journals/jsa/SelzEV96
@article{DBLP:journals/jsa/SelzEV96, author = {Manfred Selz and Wolfgang Ecker and Eugenio Villar}, title = {{VHDL} synthesis description portability: The need for Level synthesis subsets}, journal = {J. Syst. Archit.}, volume = {42}, number = {2}, pages = {105--116}, year = {1996}, url = {https://doi.org/10.1016/1383-7621(96)00017-3}, doi = {10.1016/1383-7621(96)00017-3}, timestamp = {Tue, 19 May 2020 15:54:50 +0200}, biburl = {https://dblp.org/rec/journals/jsa/SelzEV96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }

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