BibTeX record journals/integration/JahanianZS11

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@article{DBLP:journals/integration/JahanianZS11,
  author       = {Ali Jahanian and
                  Morteza Saheb Zamani and
                  Hamid Safizadeh},
  title        = {Improved predictability, timing yield and power consumption using
                  hierarchical highways-on-chip planning methodology},
  journal      = {Integr.},
  volume       = {44},
  number       = {2},
  pages        = {123--135},
  year         = {2011},
  url          = {https://doi.org/10.1016/j.vlsi.2010.10.001},
  doi          = {10.1016/J.VLSI.2010.10.001},
  timestamp    = {Thu, 20 Feb 2020 13:21:28 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/JahanianZS11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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