"Area-Efficient Selective Multi-Threshold CMOS Design Methodology for ..."

Takeshi Kitahara et al. (2007)

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DOI: —

access: open

type: Informal or Other Publication

metadata version: 2018-08-13

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  dblp key:
  - journals/corr/abs-0710-4762
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  - https://dblp.org/rec/journals/corr/abs-0710-4762
Takeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami, Katsuhiro Seta, Toshiyuki Furusawa:
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction. CoRR abs/0710.4762 (2007)

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