"A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 ..."

Raghavan Kumar et al. (2019)

> Home

Details and statistics

DOI: 10.23919/VLSIC.2019.8778041

access: closed

type: Conference or Workshop Paper

metadata version: 2022-02-25

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsic/KumarSKSAKAHCKD19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/KumarSKSAKAHCKD19
Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De, Sanu Mathew:
A 4900×m² 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition. VLSI Circuits 2019: 234-

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.