default search action
"FPGA Design of High-Speed Convolutional Neural Network Hardware Accelerator."
Ahmed J. Abd El-Maksoud et al. (2021)
- Ahmed J. Abd El-Maksoud, Abdallah Mohamed, Ahmed Tarek, Amr Adel, Amr Eid, Farida Khaled, Fatma Khaled, Ziad Ibrahim, Eman El Mandouh, Hassan Mostafa:
FPGA Design of High-Speed Convolutional Neural Network Hardware Accelerator. NILES 2021: 376-379
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.