"Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor."

Shirshendu Das, Hemangee K. Kapoor (2017)

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DOI: 10.1109/ISVLSI.2017.40

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Shirshendu Das, Hemangee K. Kapoor:
Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor. ISVLSI 2017: 182-187

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