BibTeX record conf/isscc/RusuTMAC06

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@inproceedings{DBLP:conf/isscc/RusuTMAC06,
  author       = {Stefan Rusu and
                  Simon M. Tam and
                  Harry Muljono and
                  David Ayers and
                  Jonathan Chang},
  title        = {A Dual-Core Multi-Threaded Xeon Processor with 16MB {L3} Cache},
  booktitle    = {2006 {IEEE} International Solid State Circuits Conference, {ISSCC}
                  2006, Digest of Technical Papers, an Francisco, CA, USA, February
                  6-9, 2006},
  pages        = {315--324},
  publisher    = {{IEEE}},
  year         = {2006},
  url          = {https://doi.org/10.1109/ISSCC.2006.1696062},
  doi          = {10.1109/ISSCC.2006.1696062},
  timestamp    = {Mon, 09 Aug 2021 14:54:04 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/RusuTMAC06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}