"Stack sizing analysis and optimization for FinFET logic cells and circuits ..."

Xue Lin, Yanzhi Wang, Massoud Pedram (2014)

> Home

Details and statistics

DOI: 10.1109/ISQED.2014.6783346

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-25

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isqed/LinWP14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isqed/LinWP14
Xue Lin, Yanzhi Wang, Massoud Pedram:
Stack sizing analysis and optimization for FinFET logic cells and circuits operating in the sub/near-threshold regime. ISQED 2014: 341-348

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.