"An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold ..."

Ming-Yan Tsai et al. (2018)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2018.8350985

access: closed

type: Conference or Workshop Paper

metadata version: 2018-10-24

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/TsaiKLS18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/TsaiKLS18
Ming-Yan Tsai, Po-Yu Kuo, Jin-Fa Lin, Ming-Hwa Sheu:
An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme. ISCAS 2018: 1-4

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.