BibTeX record conf/glvlsi/GaryfallouVAMS22

• > Home > conf/glvlsi/GaryfallouVAMS22

@inproceedings{DBLP:conf/glvlsi/GaryfallouVAMS22,
  author       = {Dimitrios Garyfallou and
                  Anastasis Vagenas and
                  Charalampos Antoniadis and
                  Yehia Massoud and
                  George I. Stamoulis},
  editor       = {Ioannis Savidis and
                  Avesta Sasan and
                  Himanshu Thapliyal and
                  Ronald F. DeMara},
  title        = {Leveraging Machine Learning for Gate-level Timing Estimation Using
                  Current Source Models and Effective Capacitance},
  booktitle    = {{GLSVLSI} '22: Great Lakes Symposium on {VLSI} 2022, Irvine {CA} USA,
                  June 6 - 8, 2022},
  pages        = {77--83},
  publisher    = {{ACM}},
  year         = {2022},
  url          = {https://doi.org/10.1145/3526241.3530343},
  doi          = {10.1145/3526241.3530343},
  timestamp    = {Tue, 21 Mar 2023 21:00:57 +0100},
  biburl       = {https://dblp.org/rec/conf/glvlsi/GaryfallouVAMS22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}