"Designing a virtual runtime for FPGA accelerators in the cloud."

Mikhail Asiatici et al. (2016)

> Home

Details and statistics

DOI: 10.1109/FPL.2016.7577389

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpl/AsiaticiGVFI16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpl/AsiaticiGVFI16
Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne:
Designing a virtual runtime for FPGA accelerators in the cloud. FPL 2016: 1-2

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.