BibTeX record conf/formats/FainekosGP06

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@inproceedings{DBLP:conf/formats/FainekosGP06,
  author       = {Georgios E. Fainekos and
                  Antoine Girard and
                  George J. Pappas},
  editor       = {Eugene Asarin and
                  Patricia Bouyer},
  title        = {Temporal Logic Verification Using Simulation},
  booktitle    = {Formal Modeling and Analysis of Timed Systems, 4th International Conference,
                  {FORMATS} 2006, Paris, France, September 25-27, 2006, Proceedings},
  series       = {Lecture Notes in Computer Science},
  volume       = {4202},
  pages        = {171--186},
  publisher    = {Springer},
  year         = {2006},
  url          = {https://doi.org/10.1007/11867340\_13},
  doi          = {10.1007/11867340\_13},
  timestamp    = {Tue, 07 May 2024 20:12:14 +0200},
  biburl       = {https://dblp.org/rec/conf/formats/FainekosGP06.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}