"A highly pipelined VLSI architecture for all modes and block sizes intra ..."

Cong Liu et al. (2013)

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DOI: 10.1109/ASICON.2013.6811849

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type: Conference or Workshop Paper

metadata version: 2017-07-27

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Cong Liu, Weiwei Shen, Tianlong Ma, Yibo Fan, Xiaoyang Zeng:
A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder. ASICON 2013: 1-4

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