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2020 – today
- 2024
[j24]Luis Ángel García-Astudillo
, Almudena Lindoso, Luis Entrena:
Error Mitigation Using Optimized Redundancy for Composite Algorithms in FPGAs. IEEE Trans. Aerosp. Electron. Syst. 60(2): 2143-2152 (2024)- [j23]German Leon, José M. Badía, Jose A. Belloch, Almudena Lindoso, Luis Entrena:
Comparative analysis of soft-error sensitivity in LU decomposition algorithms on diverse GPUs. J. Supercomput. 80(9): 12844-12862 (2024) - 2023
- [j22]Luis Entrena, Antonio J. Sanchez-Clemente, Luis Ángel García-Astudillo, Marta Portela-García, Mario García-Valderas, Almudena Lindoso, Roberto Sarmiento:
Formal Verification of Fault-Tolerant Hardware Designs. IEEE Access 11: 116127-116140 (2023) - [j21]Pablo M. Aviles, Jose A. Belloch, Luis Entrena, Almudena Lindoso:
Supervised Triple Macrosynchronized Lockstep (STMLS) Architecture for Multicore Processors. IEEE Access 11: 128706-128723 (2023) - [j20]Honorio Martín, Sophie Dupuis, Giorgio Di Natale, Luis Entrena:
Using Approximate Circuits Against Hardware Trojans. IEEE Des. Test 40(3): 8-16 (2023) - 2022
- [j19]Luis Ángel García-Astudillo, Luis Entrena, Almudena Lindoso, Honorio Martín:
Reduced Resolution Redundancy: A Novel Approximate Error Mitigation Technique. IEEE Access 10: 20643-20651 (2022) - [c56]Lucas Matana Luza, Frederic Wrobel, Luis Entrena, Luigi Dilillo:
Impact of Atmospheric and Space Radiation on Sensitive Electronic Devices. ETS 2022: 1-10 - 2020
- [j18]Carmen Camara, Honorio Martín, Pedro Peris-Lopez, Luis Entrena:
A True Random Number Generator Based on Gait Data for the Internet of You. IEEE Access 8: 71642-71651 (2020) - [c55]Luis Ángel García-Astudillo, Almudena Lindoso, Marta Portela, Luis Entrena:
Evaluation of a Reduced Precision Redundancy FFT Design. DCIS 2020: 1-6
2010 – 2019
- 2018
- [j17]Honorio Martín, Pedro Martín-Holgado, Pedro Peris-Lopez, Yolanda Morilla, Luis Entrena:
On the Entropy of Oscillator-Based True Random Number Generators under Ionizing Radiation. Entropy 20(7): 513 (2018) - [j16]Honorio Martín, Enrique San Millán, Luis Entrena-Arrontes:
Dynamic control of entropy and power consumption in TRNGs for IoT applications. IEICE Electron. Express 15(2): 20171157 (2018) - [j15]Manuel Peña-Fernandez, Almudena Lindoso, Luis Entrena, Mario García-Valderas, S. Philippe, Yolanda Morilla, Pedro Martín-Holgado:
PTM-based hybrid error-detection architecture for ARM microprocessors. Microelectron. Reliab. 88-90: 925-930 (2018) - [j14]Honorio Martín, Giorgio Di Natale, Luis Entrena:
Towards a Dependable True Random Number Generator With Self-Repair Capabilities. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 247-256 (2018) - [c54]Antonio Sanchez-Clemente, Luis Entrena, Fernanda Lima Kastensmidt:
Approximate TMR for selective error mitigation in FPGAs based on testability analysis. AHS 2018: 112-119 - [c53]Honorio Martín, Luis Entrena, Sophie Dupuis, Giorgio Di Natale:
A Novel Use of Approximate Circuits to Thwart Hardware Trojan Insertion and Provide Obfuscation. IOLTS 2018: 41-42 - 2016
- [j13]Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena:
Online Test of Control Flow Errors: A New Debug Interface-Based Approach. IEEE Trans. Computers 65(6): 1846-1855 (2016) - [j12]Antonio Martínez-Álvarez, Felipe Restrepo-Calle, Sergio Cuenca-Asensi, Leonardo M. Reyneri, Almudena Lindoso, Luis Entrena:
A Hardware-Software Approach for On-Line Soft Error Mitigation in Interrupt-Driven Applications. IEEE Trans. Dependable Secur. Comput. 13(4): 502-508 (2016) - [j11]Antonio Sanchez-Clemente, Luis Entrena, Radek Hrbacek, Lukás Sekanina:
Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches. IEEE Trans. Reliab. 65(4): 1871-1883 (2016) - 2014
- [j10]M. Arévalo-Garbayo, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena:
A method to assess the robustness of cryptographic circuits at the design stage. Microelectron. J. 45(10): 1354-1360 (2014) - [c52]Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena:
A new solution to on-line detection of Control Flow Errors. IOLTS 2014: 105-110 - [c51]Antonio Sanchez-Clemente, Luis Entrena, Mario García-Valderas:
Error masking with approximate logic circuits using dynamic probability estimations. IOLTS 2014: 134-139 - 2013
- [c50]Boyang Du, Matteo Sonza Reorda, Luca Sterpone, Luis Parra, Marta Portela-García, Almudena Lindoso, Luis Entrena:
Exploiting the debug interface to support on-line test of control flow errors. IOLTS 2013: 98-103 - [c49]Luis Entrena:
Fast fault injection techniques using FPGAs. LATW 2013: 1 - 2012
- [j9]Marta Portela-García, Almudena Lindoso, Luis Entrena, Mario García-Valderas, Celia López-Ongil, N. Marroni, Bernardo Pianta, Letícia Maria Bolzani Poehls, Fabian Vargas:
Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach. J. Electron. Test. 28(6): 777-789 (2012) - [j8]Marta Portela-García, Michelangelo Grosso, M. Gallardo-Campos, Matteo Sonza Reorda, Luis Entrena, Mario García-Valderas, Celia López-Ongil:
On the use of embedded debug features for permanent and transient fault resilience in microprocessors. Microprocess. Microsystems 36(5): 334-343 (2012) - [j7]Luis Entrena, Mario García-Valderas, Raúl Fernández Cardenal, Almudena Lindoso, Marta Portela-García, Celia López-Ongil:
Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection. IEEE Trans. Computers 61(3): 313-322 (2012) - [c48]Antonio Sanchez-Clemente, Luis Entrena, Mario García-Valderas, Celia López-Ongil:
Logic masking for SET Mitigation Using Approximate Logic Circuits. IOLTS 2012: 176-181 - [c47]Celia López-Ongil, Marta Portela-García, Mario García-Valderas, Anna Vaskova, Luis Entrena, Joaquín Rivas-Abalo, Alberto Martín-Ortega, Javier Martinez-Oter, S. Rodriguez-Bustabad, Ignacio Arruego:
SEU sensitivity of robust communication protocols. IOLTS 2012: 188-193 - 2011
- [j6]Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena:
Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures. IEEE Trans. Dependable Secur. Comput. 8(2): 308-314 (2011) - [c46]Anna Vaskova, Celia López-Ongil, Enrique San Millán, Alejandro Jiménez-Horas, Luis Entrena:
Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomness. IOLTS 2011: 179-181 - [c45]Honorio Martín, Enrique San Millán, Luis Entrena, Julio César Hernández Castro, Pedro Peris-Lopez:
AKARI-X: A pseudorandom number generator for secure lightweight systems. IOLTS 2011: 228-233 - [c44]Anna Vaskova, Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena:
Evaluation techniques for on-line testing of robust systems based on critical tasks distribution. IOLTS 2011: 258-263 - [c43]Marta Portela-García, Almudena Lindoso, Luis Entrena, Mario García-Valderas, Celia López-Ongil, Bernardo Pianta, Letícia Maria Bolzani Poehls, Fabian Vargas:
Using an FPGA-based fault injection technique to evaluate software robustness under SEEs: A case study. LATW 2011: 1-6 - 2010
- [c42]Pedro Peris-Lopez, Enrique San Millán, Jan C. A. van der Lubbe, Luis Entrena:
Cryptographically secure pseudo-random bit generator for RFID tags. ICITST 2010: 1-6 - [c41]Michelangelo Grosso, Matteo Sonza Reorda, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena:
An on-line fault detection technique based on embedded debug features. IOLTS 2010: 167-172 - [c40]Anna Vaskova, Celia López-Ongil, Alejandro Jiménez-Horas, Enrique San Millán, Luis Entrena:
Robust cryptographic ciphers with on-line statistical properties validation. IOLTS 2010: 208-210
2000 – 2009
- 2009
- [j5]Mario García-Valderas, Luis Entrena, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García:
SET Emulation Under a Quantized Delay Model. J. Electron. Test. 25(1): 107-116 (2009) - [c39]Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena:
In-depth analysis of digital circuits against soft errors for selective hardening. IOLTS 2009: 144-149 - [c38]Fabian Vargas, Claudia A. Rocha, Bernardo Pianta, Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena:
Briefing power/reliability optimization in embedded software design. IOLTS 2009: 185-186 - [c37]Alejandro Jiménez-Horas, Enrique San Millán, Celia López-Ongil, Marta Portela-García, Mario García-Valderas, Luis Entrena:
Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers. IOLTS 2009: 203-205 - [c36]Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena, B. Lestriez, Luis Berrojo:
Study of SEU effects in a Turbo Decoder Bit Error Rate. LATW 2009: 1-5 - 2008
- [c35]Enrique San Millán, Luis Entrena, José Alberto Espejo:
Logic Transformations by Multiple Wire Network Addition. DSD 2008: 779-786 - [c34]Almudena Lindoso, Luis Entrena, Juan Izquierdo, Judith Liu-Jimenez:
Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC. FPL 2008: 539-542 - [c33]Celia López-Ongil, Alejandro Jiménez-Horas, Marta Portela-García, Mario García-Valderas, Enrique San Millán, Luis Entrena:
Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard. IOLTS 2008: 167-168 - 2007
- [j4]Almudena Lindoso, Luis Entrena:
High performance FPGA-based image correlation. J. Real Time Image Process. 2(4): 223-233 (2007) - [j3]Michael G. Lorenz, Luis Mengibar, Enrique San Millán, Luis Entrena:
Low power data processing system with self-reconfigurable architecture. J. Syst. Archit. 53(9): 568-576 (2007) - [c32]Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez:
Wavelet-Based Fingerprint Region Selection. CAIP 2007: 391-398 - [c31]Mario García-Valderas, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García, Luis Entrena:
SET Emulation Under a Quantized Delay Model. DFT 2007: 68-77 - [c30]Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez, Enrique San Millán:
Correlation-Based Fingerprint Matching with Orientation Field Alignment. ICB 2007: 713-721 - [c29]Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena:
A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors. IOLTS 2007: 101-106 - [i1]Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes:
Techniques for Fast Transient Fault Grading Based on Autonomous Emulation. CoRR abs/0710.4757 (2007) - 2006
- [c28]Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena-Arrontes:
An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories. DDECS 2006: 218-219 - [c27]Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena:
Fault Injection-based Reliability Evaluation of SoPCs. ETS 2006: 75-82 - [c26]Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena:
Emulation-based Fault Injection in Circuits with Embedded Memories. IOLTS 2006: 183-184 - 2005
- [c25]Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes:
Techniques for Fast Transient Fault Grading Based on Autonomous Emulation. DATE 2005: 308-309 - [c24]Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes:
An Autonomous FPGA-based Emulation System for Fast Fault Tolerant Evaluation. FPL 2005: 397-402 - [c23]Almudena Lindoso, Luis Entrena, Celia López-Ongil, Judith Liu-Jimenez:
Correlation-Based Fingerprint Matching Using FPGAs. FPT 2005: 87-94 - [c22]Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes:
Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading. IOLTS 2005: 43-48 - 2004
- [c21]Raul Sánchez-Reillo, Judith Liu-Jimenez, Luis Entrena:
Architectures for Biometric Match-on-Token Solutions. ECCV Workshop BioAW 2004: 195-204 - [c20]Celia López-Ongil, Raul Sánchez-Reillo, Judith Liu-Jimenez, Fernando Casado, Leslie Sánchez, Luis Entrena:
FPGA Implementation of Biometric Authentication System Based on Hand Geometry. FPL 2004: 43-53 - [c19]Michael G. Lorenz, Luis Mengibar, Mario García-Valderas, Luis Entrena:
Power Consumption Reduction Through Dynamic Reconfiguration. FPL 2004: 751-760 - [c18]Mario García-Valderas, Celia López-Ongil, Marta Portela-García, Luis Entrena:
Transient Fault Emulation of Hardened Circuits in FPGA Platforms. IOLTS 2004: 109-114 - 2003
- [j2]Enrique San Millán, Luis Entrena, José Alberto Espejo, Celia López:
Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques. J. Syst. Archit. 49(12-15): 529-541 (2003) - [c17]Michael G. Lorenz, Luis Mengibar, Luis Entrena, Raul Sánchez-Reillo:
Data Processing System With Self-reconfigurable Architecture, for Low Cost, Low Power Applications. FPL 2003: 220-229 - [c16]Luis Mengibar, Luis Entrena, Michael G. Lorenz, Raul Sánchez-Reillo:
State Encoding for Low-Power FSMs in FPGA. PATMOS 2003: 31-40 - 2002
- [c15]Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López:
New Techniques for Speeding-Up Fault-Injection Campaigns. DATE 2002: 847-852 - [c14]Luis Berrojo, Isabel González, Luis Entrena, Celia López, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero:
Analysis of the Equivalences and Dominances of Transient Faults at the RT Level. IOLTW 2002: 193 - [c13]Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López:
An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation. VTS 2002: 229-236 - 2001
- [c12]José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías:
Functional extension of structural logic optimization techniques. ASP-DAC 2001: 467-472 - [c11]José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías:
Generalized reasoning scheme for redundancy addition and removal logic optimization. DATE 2001: 391-397 - [c10]Enrique San Millán, Luis Entrena, José Alberto Espejo:
On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. DSD 2001: 292-299 - [c9]Enrique San Millán, Luis Entrena, José Alberto Espejo:
On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits. ICCAD 2001: 91-94 - [c8]Luis Entrena, Celia López, Emilio Olías, Enrique San Millán, José Alberto Espejo:
Logic Optimization of Unidirectional Circuits with Structural Methods. IOLTW 2001: 43-47 - [c7]Luis Entrena, Celia López, Emilio Olías:
Automatic Insertion of Fault-Tolerant Structures at the RT Level. IOLTW 2001: 48-50
1990 – 1999
- 1999
- [c6]Enrique San Millán, Luis Entrena, José Alberto Espejo, Silvia Chiusano, Fulvio Corno:
Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization. DATE 1999: 516-520 - [c5]José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías:
Logic Restructuring for MUX-Based FPGAs. EUROMICRO 1999: 1161- - 1996
- [c4]Luis Entrena, Emilio Olías, Javier Uceda, José Alberto Espejo:
Timing optimization by an improved redundancy addition and removal technique. EURO-DAC 1996: 342-347 - 1995
- [j1]Luis Entrena-Arrontes, Kwang-Ting Cheng:
Combinational and sequential logic optimization by redundancy addition and removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(7): 909-916 (1995) - [c3]Serafín Olcoz, Luis Entrena, Luis Berrojo:
An effective system development environment based on VHDL prototyping. EURO-DAC 1995: 502-507 - [c2]Serafín Olcoz, Luis Entrena, Luis Berrojo:
VHDL virtual prototyping. RSP 1995: 161-167 - 1993
- [c1]Luis Entrena, Kwang-Ting Cheng:
Sequential logic optimization by redundancy addition and removal. ICCAD 1993: 310-315
Coauthor Index
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last updated on 2024-08-05 20:19 CEST by the dblp team
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