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ORCIDJacob A. Abraham
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- affiliation: University of Texas at Austin, USA
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2020 – today
- 2023
[c328]Kwondo Ma, Chandramouli N. Amarnath, Abhijit Chatterjee, Jacob A. Abraham:
Secure Control Loop Execution of Cyber-Physical Devices Using Predictive State Space Checks. ISQED 2023: 1-8- 2022
- [j113]Laith Mohammad Abualigah
, Mohammad Shehab, Ali Diabat, Jacob A. Abraham:
Selection scheme sensitivity for a hybrid Salp Swarm Algorithm: analysis and applications. Eng. Comput. 38(2): 1149-1175 (2022) - 2021
- [j112]Phuoc Pham, Jacob A. Abraham, Jaeyong Chung:
Training Multi-Bit Quantized and Binarized Networks with a Learnable Symmetric Quantizer. IEEE Access 9: 47194-47203 (2021) - [j111]Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham:
A Current and Temperature Limiting System in a 7-nm Hexagon™ Compute Digital Signal Processor. IEEE J. Solid State Circuits 56(3): 814-823 (2021) - [j110]Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham:
A Proactive System for Voltage-Droop Mitigation in a 7-nm Hexagon™ Processor. IEEE J. Solid State Circuits 56(4): 1166-1175 (2021) - [j109]Suvadeep Banerjee, Balavinayagam Samynathan, Jacob A. Abraham, Abhijit Chatterjee:
Real-Time Error Detection in Nonlinear Control Systems Using Machine Learning Assisted State-Space Encoding. IEEE Trans. Dependable Secur. Comput. 18(2): 576-592 (2021) - [i3]Phuoc Pham, Jacob A. Abraham, Jaeyong Chung:
Training Multi-bit Quantized and Binarized Networks with A Learnable Symmetric Quantizer. CoRR abs/2104.00210 (2021) - 2020
- [j108]Byoungho Kim, Jacob A. Abraham:
Built-in Harmonic Prediction Scheme for Embedded Segmented-Data-Converters. IEEE Access 8: 7851-7860 (2020) - [c327]Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham:
Randomized Pulse-Modulating Instruction-Issue Control Circuit for a Current and Temperature Limiting System in a 7nm Hexagon™ Compute DSP. CICC 2020: 1-4 - [c326]Vijay Kiran Kalyanam, Eric Mahurin, Michael Spence, Jacob A. Abraham:
Functional Test Sequences for Inducing Voltage Droops in a Multi-Threaded Processor. ITC 2020: 1-10 - [c325]Vijay Kiran Kalyanam, Eric Mahurin, Keith A. Bowman, Jacob A. Abraham:
A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon™ Processor. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j107]Jie Fang, Chaoming Zhang, Frank Singor, Jacob A. Abraham:
A Broadband CMOS RF Front End for Direct Sampling Satellite Receivers. IEEE J. Solid State Circuits 54(8): 2140-2148 (2019) - [j106]Byoungho Kim, Jacob A. Abraham:
Spectral Leakage-Driven Loopback Scheme for Prediction of Mixed-Signal Circuit Specifications. IEEE Trans. Ind. Electron. 66(1): 586-594 (2019) - [c324]Eric Cheng, Daniel Mueller-Gritschneder, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Deming Chen, Hyungmin Cho, Yanjing Li, Uzair Sharif, Kevin Skadron, Mircea Stan, Ulf Schlichtmann, Subhasish Mitra:
Cross-Layer Resilience: Challenges, Insights, and the Road Ahead. DAC 2019: 198 - [c323]Jacob A. Abraham:
Resiliency Demands on Next Generation Critical Embedded Systems. IOLTS 2019: 135-138 - 2018
- [j105]Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra:
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1839-1852 (2018) - [c322]Ameya Chaudhari, Jacob A. Abraham:
Effective Control Flow Integrity Checks for Intrusion Detection. IOLTS 2018: 103-108 - [c321]Ninghan Tian, Daniel G. Saab, Jacob A. Abraham:
ESIFT: Efficient System for Error Injection. IOLTS 2018: 201-206 - [c320]Md Imran Momtaz, Suvadeep Banerjee, Sujay Pandey, Jacob A. Abraham, Abhijit Chatterjee:
Cross-Layer Control Adaptation for Autonomous System Resilience. IOLTS 2018: 261-264 - 2017
- [j104]Jie Fang, Shankar Thirunakkarasu, Xuefeng Yu, Fabian Silva-Rivas, Chaoming Zhang, Frank Singor, Jacob A. Abraham:
A 5-GS/s 10-b 76-mW Time-Interleaved SAR ADC in 28 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(7): 1673-1683 (2017) - [c319]Eric Cheng, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Keith A. Campbell, Deming Chen, Chen-Yong Cher, Hyungmin Cho, Binh Q. Le, Klas Lilja, Shahrzad Mirkhani, Kevin Skadron, Mircea Stan, Lukasz G. Szafaryn, Christos Vezyrtzis, Subhasish Mitra:
Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights. ICCD 2017: 593-596 - [c318]Jacob A. Abraham, Suvadeep Banerjee, Abhijit Chatterjee:
Design of efficient error resilience in signal processing and control systems: From algorithms to circuits. IOLTS 2017: 192-195 - [c317]Vijay Kiran Kalyanam, Peter G. Sassone, Jacob A. Abraham:
Power prediction of embedded scalar and vector processor: Challenges and solutions. ISQED 2017: 221-228 - [c316]Tong Zhang, Daniel G. Saab, Jacob A. Abraham:
Automatic Assertion Generation for Simulation, Formal Verification and Emulation. ISVLSI 2017: 471-476 - [i2]Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra:
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience). CoRR abs/1709.09921 (2017) - 2016
- [j103]Immanuel Raja, Gaurab Banerjee, Mohamad A. Zeidan, Jacob A. Abraham:
A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1975-1983 (2016) - [c315]Shih-Hsin Hu, Jacob A. Abraham:
Quality Aware Error Detection in 2-D Separable Linear Transformation. ATS 2016: 257-262 - [c314]Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra:
Clear: cross-layer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores. DAC 2016: 68:1-68:6 - [c313]Jacob A. Abraham:
Cross-layer resilience: are high-level techniques always better? HLDVT 2016: 78 - [c312]Suvadeep Banerjee, Abhijit Chatterjee, Jacob A. Abraham:
Efficient cross-layer concurrent error detection in nonlinear control systems using mapped predictive check states. ITC 2016: 1-10 - [c311]Harini Bhamidipati, Daniel G. Saab, Jacob A. Abraham:
Single Trojan injection model generation and detection. LATS 2016: 181 - [c310]Suvadeep Banerjee, Abhijit Chatterjee, Jacob A. Abraham:
Checksum based error detection in linearized representations of non linear control systems. LATS 2016: 182 - [c309]Jacob A. Abraham, Abhijit Chatterjee:
Design of Self Calibrating and Error Resilient Mixed-Signal Systems for Signal Processing, Communications and Control. VLSID 2016: 1-2 - [c308]Andrzej J. Strojwas, Jacob A. Abraham, Hong Hao, Max M. Shulaker:
Keynote address: Challenges and opportunities in electrical characterization and test for 14nm and below. VTS 2016: 1-2 - [i1]Eric Cheng, Shahrzad Mirkhani, Lukasz G. Szafaryn, Chen-Yong Cher, Hyungmin Cho, Kevin Skadron, Mircea R. Stan, Klas Lilja, Jacob A. Abraham, Pradip Bose, Subhasish Mitra:
CLEAR: Cross-Layer Exploration for Architecting Resilience - Combining Hardware and Software Techniques to Tolerate Soft Errors in Processor Cores. CoRR abs/1604.03062 (2016) - 2015
- [j102]Hsun-Cheng Lee, Jacob A. Abraham:
Digital Calibration for 8-bit Delay Line ADC Using Harmonic Distortion Correction. J. Electron. Test. 31(2): 127-138 (2015) - [j101]Eun Jung Jang, Jaeyong Chung, Jacob A. Abraham:
Delay Defect Diagnosis Methodology Using Path Delay Measurements. IEICE Trans. Electron. 98-C(10): 991-994 (2015) - [c307]Shahrzad Mirkhani, Subhasish Mitra, Chen-Yong Cher, Jacob A. Abraham:
Efficient soft error vulnerability estimation of complex designs. DATE 2015: 103-108 - [c306]Gregory Ford, Aswin Krishna, Jacob A. Abraham, Daniel G. Saab:
Formal Verification ATPG Search Engine Emulator (Abstract Only). FPGA 2015: 264 - [c305]Vijay Kiran Kalyanam, Martin Saint-Laurent, Jacob A. Abraham:
Power-aware multi-voltage custom memory models for enhancing RTL and low power verification. ICCD 2015: 24-31 - [c304]Jacob A. Abraham, Ravishankar K. Iyer, Dimitris Gizopoulos, Dan Alexandrescu, Yervant Zorian:
The future of fault tolerant computing. IOLTS 2015: 108-109 - [c303]Jacob A. Abraham, Abhijit Chatterjee:
Tutorial T3: Error Resilient Real-Time Embedded Systems: Computing, Communications and Control. VLSID 2015: 6-7 - [c302]Shahrzad Mirkhani, Balavinayagam Samynathan, Jacob A. Abraham:
In-depth soft error vulnerability analysis using synthetic benchmarks. VTS 2015: 1-6 - 2014
- [j100]Marc Snir, Robert W. Wisniewski, Jacob A. Abraham, Sarita V. Adve, Saurabh Bagchi, Pavan Balaji, James F. Belak, Pradip Bose, Franck Cappello, Bill Carlson, Andrew A. Chien, Paul Coteus, Nathan DeBardeleben, Pedro C. Diniz, Christian Engelmann, Mattan Erez, Saverio Fazzari, Al Geist, Rinku Gupta, Fred Johnson, Sriram Krishnamoorthy, Sven Leyffer, Dean Liberty, Subhasish Mitra, Todd S. Munson, Rob Schreiber, Jon Stearley, Eric Van Hensbergen:
Addressing failures in exascale computing. Int. J. High Perform. Comput. Appl. 28(2): 129-173 (2014) - [j99]Byoungho Kim, Jacob A. Abraham:
Dynamic Performance Characterization of Embedded Single-Ended Mixed-Signal Circuits. IEEE Trans. Circuits Syst. II Express Briefs 61-II(5): 329-333 (2014) - [j98]Byoungho Kim, Jacob A. Abraham:
Bitstream-Driven Built-In Characterization for Analog and Mixed-Signal Embedded Circuits. IEEE Trans. Circuits Syst. II Express Briefs 61-II(10): 743-747 (2014) - [c301]Shahrzad Mirkhani, Hyungmin Cho, Subhasish Mitra, Jacob A. Abraham:
Rethinking error injection for effective resilience. ASP-DAC 2014: 390-393 - [c300]Suvadeep Banerjee, Álvaro Gómez-Pau, Abhijit Chatterjee, Jacob A. Abraham:
Error Resilient Real-Time State Variable Systems for Signal Processing and Control. ATS 2014: 39-44 - [c299]Hsun-Cheng Lee, Jacob A. Abraham:
A novel low power 11-bit hybrid ADC using flash and delay line architectures. DATE 2014: 1-4 - [c298]Ulf Schlichtmann, Veit Kleeberger, Jacob A. Abraham, Adrian Evans, Christina Gimmler-Dumont, Michael Glaß, Andreas Herkersdorf, Sani R. Nassif, Norbert Wehn:
Connecting different worlds - Technology abstraction for reliability-aware design and Test. DATE 2014: 1-8 - [c297]Shakeel S. Abdulla, Haewoon Nam, Jacob A. Abraham:
A novel algorithm for sparse FFT pruning and its applications to OFDMA technology. IPCCC 2014: 1-7 - [c296]Shahrzad Mirkhani, Jacob A. Abraham:
EAGLE: A regression model for fault coverage estimation using a simulation based metric. ITC 2014: 1-10 - [c295]Hsun-Cheng Lee, Jacob A. Abraham:
Harmonic distortion correction for 8-bit delay line ADC using gray code. LATW 2014: 1-4 - [c294]Jacob A. Abraham, Xinli Gu, Teresa MacLaurin, Janusz Rajski, Paul G. Ryan, Dimitris Gizopoulos, Matteo Sonza Reorda:
Special session 8B - Panel: In-field testing of SoC devices: Which solutions by which players? VTS 2014: 1-2 - [c293]Shahrzad Mirkhani, Jacob A. Abraham:
Fast evaluation of test vector sets using a simulation-based statistical metric. VTS 2014: 1-6 - 2013
- [j97]Byoungho Kim, Jacob A. Abraham:
Capacitor-Coupled Built-Off Self-Test in Analog and Mixed-Signal Embedded Systems. IEEE Trans. Circuits Syst. II Express Briefs 60-II(5): 257-261 (2013) - [j96]Mohamad A. Zeidan, Gaurab Banerjee, Jacob A. Abraham:
Asynchronous Measurement of Transient Phase-Shift Resulting From RF Receiver State-Change. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(10): 2740-2751 (2013) - [j95]Jaeyong Chung, Joonsung Park, Jacob A. Abraham:
A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 281-291 (2013) - [j94]Jaeyong Chung, Jacob A. Abraham:
Concurrent Path Selection Algorithm in Statistical Timing Analysis. IEEE Trans. Very Large Scale Integr. Syst. 21(9): 1715-1726 (2013) - [c292]Hsun-Cheng Lee, Jacob A. Abraham:
Digital Calibration for 8-Bit Delay Line ADC Using Harmonic Distortion Correction. Asian Test Symposium 2013: 128-133 - [c291]Hyungmin Cho, Shahrzad Mirkhani, Chen-Yong Cher, Jacob A. Abraham, Subhasish Mitra:
Quantitative evaluation of soft error injection techniques for robust system design. DAC 2013: 101:1-101:10 - [c290]Junyoung Park, Ameya Chaudhari, Jacob A. Abraham:
Non-speculative double-sampling technique to increase energy-efficiency in a high-performance processor. DATE 2013: 254-257 - [c289]Suvadeep Banerjee, Aritra Banerjee, Abhijit Chatterjee, Jacob A. Abraham:
Real-time checking of linear control systems using analog checksums. IOLTS 2013: 122-127 - [c288]Vinod Viswanath, Rajeev Muralidhar, Harinarayanan Seshadri, Jacob A. Abraham:
On a rewriting strategy for dynamically managing power constraints and power dissipation in SoCs. ISQED 2013: 128-134 - [c287]Mahesh Prabhu, Jacob A. Abraham:
Application of under-approximation techniques to functional test generation targeting hard to detect stuck-at faults. ITC 2013: 1-7 - [c286]Kihyuk Han, Joon-Sung Yang, Jacob A. Abraham:
Dynamic Trace Signal Selection for Post-Silicon Validation. VLSI Design 2013: 302-307 - [c285]Ameya Chaudhari, Junyoung Park, Jacob A. Abraham:
A framework for low overhead hardware based runtime control flow error detection and recovery. VTS 2013: 1-6 - [c284]Kihyuk Han, Joon-Sung Yang, Jacob A. Abraham:
Enhanced algorithm of combining trace and scan signals in post-silicon validation. VTS 2013: 1-6 - [c283]Takahiro J. Yamaguchi, Jacob A. Abraham, Gordon W. Roberts, Suriyaprakash Natarajan, Dennis J. Ciplickas:
Special session 12B: Panel post-silicon validation & test in huge variance era. VTS 2013: 1 - 2012
- [j93]Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham:
Built-in Self Test of RF Subsystems with Integrated Detectors. J. Electron. Test. 28(5): 557-569 (2012) - [j92]Hyunjin Kim, Jacob A. Abraham:
A Built-in Self-Test Scheme for Memory Interfaces Timing Test and Measurement. J. Electron. Test. 28(5): 585-597 (2012) - [j91]Sachin Dileep Dasnurkar, Jacob A. Abraham:
Calibration Enabled Scalable Current Sensor Module for Quiescent Current Testing. J. Electron. Test. 28(5): 697-704 (2012) - [j90]Xiao Pu, Krishnaswamy Nagaraj, Jacob A. Abraham, Axel Thomsen:
A Novel fractional-n PLL Based on a Simple Reference Multiplier. J. Circuits Syst. Comput. 21(6) (2012) - [j89]Vinod Viswanath, Jacob A. Abraham:
Automatic and Correct Register Transfer Level Annotations for Low Power Microprocessor Design. J. Low Power Electron. 8(4): 424-439 (2012) - [j88]Baker Mohammad, Jacob A. Abraham:
A reduced voltage swing circuit using a single supply to enable lower voltage operation for SRAM-based memory. Microelectron. J. 43(2): 110-118 (2012) - [j87]Jaeyong Chung, Jacob A. Abraham:
Refactoring of Timing Graphs and Its Use in Capturing Topological Correlation in SSTA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(4): 485-496 (2012) - [j86]Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham:
Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(4): 497-508 (2012) - [j85]Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham:
Testability-Driven Statistical Path Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(8): 1275-1287 (2012) - [j84]Jaeyong Chung, Jacob A. Abraham:
On Computing Criticality in Refactored Timing Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1935-1939 (2012) - [j83]Mohamad A. Zeidan, Gaurab Banerjee, Ranjit Gharpurey, Jacob A. Abraham:
Phase-Aware Multitone Digital Signal Based Test for RF Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(9): 2097-2110 (2012) - [j82]Byoungho Kim, Jacob A. Abraham:
Imbalance-Based Self-Test for High-Speed Mixed-Signal Embedded Systems. IEEE Trans. Circuits Syst. II Express Briefs 59-II(11): 785-789 (2012) - [c282]Hyunjin Kim, Jacob A. Abraham:
On-chip source synchronous interface timing test scheme with calibration. DATE 2012: 1146-1149 - [c281]Jae Wook Lee, Ji Hwan (Paul) Chun, Jacob A. Abraham:
Indirect method for random jitter measurement on SoCs using critical path characterization. ETS 2012: 1-6 - [c280]Mahesh Prabhu, Jacob A. Abraham:
Functional test generation for hard to detect stuck-at faults using RTL model checking. ETS 2012: 1-6 - [c279]Ameya Chaudhari, Jacob A. Abraham:
Stream cipher hash based execution monitoring (SCHEM) framework for intrusion detection on embedded processors. IOLTS 2012: 162-167 - [c278]Shahrzad Mirkhani, Jacob A. Abraham, Toai Vo, Hong Shin Jun, Bill Eklow:
FALCON: Rapid statistical fault coverage estimation for complex designs. ITC 2012: 1-10 - [c277]Junyoung Park, H. Mert Ustun, Jacob A. Abraham:
Run-time Prediction of the Optimal Performance Point in DVS-based Dynamic Thermal Management. VLSI Design 2012: 155-160 - [c276]Hyunjin Kim, Jacob A. Abraham:
A Built-In Self-Test scheme for DDR memory output timing test and measurement. VTS 2012: 7-12 - [c275]Eun Jung Jang, Anne Gattiker, Sani R. Nassif, Jacob A. Abraham:
An oscillation-based test structure for timing information extraction. VTS 2012: 74-79 - [c274]Ji Hwan (Paul) Chun, Siew Mooi Lim, Shao Chee Ong, Jae Wook Lee, Jacob A. Abraham:
Test of phase interpolators in high speed I/Os using a sliding window search. VTS 2012: 134-139 - [c273]Junyoung Park, Jacob A. Abraham:
An aging-aware flip-flop design based on accurate, run-time failure prediction. VTS 2012: 294-299 - 2011
- [j81]Joonsung Park, Hongjoong Shin, Jacob A. Abraham:
Pseudorandom Test of Nonlinear Analog and Mixed-Signal Circuits Based on a Volterra Series Model. J. Electron. Test. 27(3): 321-334 (2011) - [j80]Kihyuk Han, Joonsung Park, Jae Wook Lee, Jaeyong Chung, Eonjo Byun, Cheol-Jong Woo, Sejang Oh, Jacob A. Abraham:
Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip. J. Electron. Test. 27(4): 429-439 (2011) - [j79]Ramtilak Vemu, Jacob A. Abraham:
CEDA: Control-Flow Error Detection Using Assertions. IEEE Trans. Computers 60(9): 1233-1245 (2011) - [j78]Byoungho Kim, Jacob A. Abraham:
Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(8): 1773-1784 (2011) - [j77]Byoungho Kim, Jacob A. Abraham:
Transformer-Coupled Loopback Test for Differential Mixed-Signal Dynamic Specifications. IEEE Trans. Instrum. Meas. 60(6): 2014-2024 (2011) - [c272]Joonsoo Kim, Joonsoo Lee, Jacob A. Abraham:
System accuracy estimation of SRAM-based device authentication. ASP-DAC 2011: 37-42 - [c271]Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham:
Path criticality computation in parameterized statistical timing analysis. ASP-DAC 2011: 249-254 - [c270]Tung-Yeh Wu, Shih-Hsin Hu, Jacob A. Abraham:
Robust power gating reactivation by dynamic wakeup sequence throttling. ASP-DAC 2011: 615-620 - [c269]Hyunjin Kim, Jacob A. Abraham:
On-Chip Programmable Dual-Capture for Double Data Rate Interface Timing Test. Asian Test Symposium 2011: 15-20 - [c268]Eun Jung Jang, Jaeyong Chung, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham:
Post-Silicon Timing Validation Method Using Path Delay Measurements. Asian Test Symposium 2011: 232-237 - [c267]Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham:
Testability driven statistical path selection. DAC 2011: 417-422 - [c266]Junyoung Park, Jacob A. Abraham:
A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems. ISLPED 2011: 391-396 - [c265]Jacob A. Abraham:
Tutorial: "Manufacturing test of systems-on-a-chip (SoCs)". SoCC 2011: 272 - [c264]Eun Jung Jang, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham:
Efficient and product-representative timing model validation. VTS 2011: 90-95 - 2010
- [j76]Hongjoong Shin, Joonsung Park, Jacob A. Abraham:
Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits. J. Electron. Test. 26(1): 73-86 (2010) - [j75]Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham:
On-Chip Delay Measurement Based Response Analysis for Timing Characterization. J. Electron. Test. 26(6): 599-619 (2010) - [c263]Ji Hwan (Paul) Chun, Jae Wook Lee, Jacob A. Abraham:
A novel characterization technique for high speed I/O mixed signal circuit components using random jitter injection. ASP-DAC 2010: 312-317 - [c262]Hyunjin Kim, Jacob A. Abraham:
A Low Cost Built-In Self-Test Circuit for High-Speed Source Synchronous Memory Interfaces. Asian Test Symposium 2010: 123-128 - [c261]Joonsung Park, Jae Wook Lee, Jaeyong Chung, Kihyuk Han, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo, Sejang Oh:
At-speed Test of High-Speed DUT Using Built-Off Test Interface. Asian Test Symposium 2010: 269-274 - [c260]Sachin Dileep Dasnurkar, Jacob A. Abraham:
Calibration-enabled scalable built-in current sensor compatible with very low cost ATE. ETS 2010: 119-124 - [c259]Hyunjin Kim, Jaeyong Chung, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo:
A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge control. ETS 2010: 145-150 - [c258]Jae Wook Lee, Ji Hwan (Paul) Chun, Jacob A. Abraham:
A delay measurement method using a shrinking clock signal. ACM Great Lakes Symposium on VLSI 2010: 139-142 - [c257]Joonsoo Kim, Joonsoo Lee, Jacob A. Abraham:
Toward reliable SRAM-based device identification. ICCD 2010: 313-320 - [c256]Jagdish Chandra Patra, Jacob A. Abraham, Pramod Kumar Meher, Goutam Chakraborty:
An improved SOM-based visualization technique for DNA microarray data analysis. IJCNN 2010: 1-7 - [c255]Sachin Dileep Dasnurkar, Jacob A. Abraham:
Real-time dynamic hybrid BiST solution for Very-Low-Cost ATE production testing of A/D converters with controlled DPPM. ISQED 2010: 562-569 - [c254]Shakeel S. Abdulla, Haewoon Nam, Earl E. Swartzlander Jr., Jacob A. Abraham:
High speed recursion-free CORDIC architecture. SoCC 2010: 65-70 - [c253]Tung-Yeh Wu, Sriram Sambamurthy, Jacob A. Abraham:
Estimation of maximum application-level power supply noise. SoCC 2010: 213-218 - [c252]Jaeyong Chung, Joonsung Park, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo:
Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rate. VTS 2010: 33-38 - [c251]Mohamad A. Zeidan, Aritra Banerjee, Ranjit Gharpurey, Jacob A. Abraham:
Multitone digital signal based test for RF receivers. VTS 2010: 343-348
2000 – 2009
- 2009
- [j74]Rajeshwary Tayade, Jacob A. Abraham:
Critical Path Selection for Delay Testing Considering Coupling Noise. J. Electron. Test. 25(4-5): 213-223 (2009) - [j73]Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham:
Dedicated Rewriting: Automatic Verification of Low Power Transformations in Register Transfer Level. J. Low Power Electron. 5(3): 339-353 (2009) - [c250]Jae Wook Lee, Ji Hwan (Paul) Chun, Jacob A. Abraham:
A Random Jitter RMS Estimation Technique for BIST Applications. Asian Test Symposium 2009: 9-14 - [c249]Joonsung Park, Jaeyong Chung, Jacob A. Abraham:
LFSR-Based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits. Asian Test Symposium 2009: 373-378 - [c248]Shih-Hsin Hu, Tung-Yeh Wu, Jacob A. Abraham:
SNR-Aware Error Detection for Low-Power Discrete Wavelet Lifting Transform in JPEG 2000. DFT 2009: 136-144 - [c247]Kihyuk Han, Joonsung Park, Jae Wook Lee, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo, Sejang Oh:
Low-Complexity Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip. ETS 2009: 129-134 - [c246]Rajeshwary Tayade, Jacob A. Abraham:
Critical Path Selection for Delay Test Considering Coupling Noise. ETS 2009: 163-168 - [c245]Jaeyong Chung, Jacob A. Abraham:
A hierarchy of subgraphs underlying a timing graph and its use in capturing topological correlation in SSTA. ICCAD 2009: 321-327 - [c244]Shakeel S. Abdulla, Haewoon Nam, Mark McDermot, Jacob A. Abraham:
A high throughput FFT processor with no multipliers. ICCD 2009: 485-490 - [c243]Abhijit Chatterjee, Jacob A. Abraham, Adit D. Singh, Elie Maricau, Rakesh Kumar, Christos A. Papachristou:
Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?. IOLTS 2009: 129 - [c242]Shih-Hsin Hu, Jacob A. Abraham:
Error detection in 2-D Discrete Wavelet lifting transforms. IOLTS 2009: 170-175 - [c241]Sachin Dileep Dasnurkar, Jacob A. Abraham:
Hybrid BiST Solution for Analog to Digital Converters with Low-cost Automatic Test Equipment Compatibility. ISCAS 2009: 9-12 - [c240]Tung-Yeh Wu, Samaneh Gharahi, Jacob A. Abraham:
An Area Efficient On-chip Static IR Drop Detector/Evaluator. ISCAS 2009: 2009-2012 - [c239]Savithri Sundareswaran, Rajendran Panda, Jacob A. Abraham, Yun Zhang, Amit Mittal:
Characterization of sequential cells for constraint sensitivities. ISQED 2009: 74-79 - [c238]Sriram Sambamurthy, Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham:
Functionally valid gate-level peak power estimation for processors. ISQED 2009: 753-758 - [c237]Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham:
Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL. VLSI Design 2009: 77-82 - [c236]Jaeyong Chung, Jacob A. Abraham:
Recursive Path Selection for Delay Fault Testing. VTS 2009: 65-70 - [c235]Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham:
On-Line Calibration and Power Optimization of RF Systems Using a Built-In Detector. VTS 2009: 285-290 - 2008
- [j72]Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraham, Jiajin Tu:
Sequential equivalence checking between system level and RTL descriptions. Des. Autom. Embed. Syst. 12(4): 377-396 (2008) - [j71]Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka:
Performance-Optimized Design for Parametric Reliability. J. Electron. Test. 24(1-3): 129-141 (2008) - [j70]Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu:
Controllability of Static CMOS Circuits for Timing Characterization. J. Electron. Test. 24(5): 481-496 (2008) - [j69]Rajeshwary Tayade, Jacob A. Abraham:
Small-delay defect detection in the presence of process variations. Microelectron. J. 39(8): 1093-1100 (2008) - [c234]Rajeshwary Tayade, Sani R. Nassif, Jacob A. Abraham:
Analytical model for the impact of multiple input switching noise on timing. ASP-DAC 2008: 514-517 - [c233]Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche:
A low-cost concurrent error detection technique for processor control logic. DATE 2008: 897-902 - [c232]Jacob A. Abraham:
Implications of Technology Trends on System Dependability. DATE 2008: 940 - [c231]Neeraj Suri, Christof Fetzer, Jacob A. Abraham, Stefan Poledna, Avi Mendelson, Subhasish Mitra:
Dependable Embedded Systems Special Day Panel: Issues and Challenges in Dependable Embedded Systems. DATE 2008: 1394-1395 - [c230]Rajeshwary Tayade, Jacob A. Abraham:
Critical Path Selection for Delay Test Considering Coupling Noise. ETS 2008: 119-124 - [c229]Qingqi Dou, Jacob A. Abraham:
Jitter Decomposition in High-Speed Communication Systems. ETS 2008: 157-162 - [c228]Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Suriyaprakash Natarajan:
On efficient generation of instruction sequences to test for delay defects in a processor. ACM Great Lakes Symposium on VLSI 2008: 279-284 - [c227]Baker Mohammad, Stephen Bijansky, Adnan Aziz, Jacob A. Abraham:
Adaptive SRAM memory for low power and high yield. ICCD 2008: 176-181 - [c226]Ramtilak Vemu, Jacob A. Abraham:
Budget-Dependent Control-Flow Error Detection. IOLTS 2008: 73-78 - [c225]Baker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob A. Abraham:
Cache Design for Low Power and High Yield. ISQED 2008: 103-107 - [c224]Savithri Sundareswaran, Jacob A. Abraham, Alexandre Ardelea, Rajendran Panda:
Characterization of Standard Cells for Intra-Cell Mismatch Variations. ISQED 2008: 213-219 - [c223]Xiao Pu, Axel Thomsen, Jacob A. Abraham:
Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLL. ISVLSI 2008: 168-172 - [c222]Rajeshwary Tayade, Jacob A. Abraham:
On-chip Programmable Capture for Accurate Path Delay Test and Characterization. ITC 2008: 1-10 - [c221]Savithri Sundareswaran, Lucie Nechanicka, Rajendran Panda, Sergey Gavrilov, Roman A. Solovyev, Jacob A. Abraham:
A timing methodology considering within-die clock skew variations. SoCC 2008: 351-356 - [c220]Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri:
A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits. VLSI Design 2008: 521-526 - [c219]Qingqi Dou, Jacob A. Abraham:
Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems. VTS 2008: 3-8 - [c218]Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham:
Low Cost RF Receiver Parameter Measurement with On-Chip Amplitude Detectors. VTS 2008: 203-208 - [c217]Byoungho Kim, Nash Khouzam, Jacob A. Abraham:
Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits. VTS 2008: 293-298 - [c216]Joonsung Park, Hongjoong Shin, Jacob A. Abraham:
Parallel Loopback Test of Mixed-Signal Circuits. VTS 2008: 309-316 - 2007
- [j68]Byoungho Kim, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham:
Predicting mixed-signal dynamic performance using optimised signature-based alternate test. IET Comput. Digit. Tech. 1(3): 159-169 (2007) - [j67]Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham:
Improved verification of hardware designs through antecedent conditioned slicing. Int. J. Softw. Tools Technol. Transf. 9(1): 89-101 (2007) - [j66]Shobha Vasudevan, Vinod Viswanath, Robert W. Sumners, Jacob A. Abraham:
Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems. IEEE Trans. Computers 56(10): 1401-1414 (2007) - [c215]Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Daniel G. Saab:
Automatic Generation of Instructions to Robustly Test Delay Defects in Processors. ETS 2007: 173-178 - [c214]Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob A. Abraham:
Estimating path delay distribution considering coupling noise. ACM Great Lakes Symposium on VLSI 2007: 61-66 - [c213]Jen-Chieh Ou, Daniel G. Saab, Qiang Qiang, Jacob A. Abraham:
Reducing verification overhead with RTL slicing. ACM Great Lakes Symposium on VLSI 2007: 399-404 - [c212]Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham:
Built-In Test of RF Mixers Using RF Amplitude Detectors. ISQED 2007: 404-409 - [c211]Joonsung Park, Hongjoong Shin, Jacob A. Abraham:
Pseudorandom Test for Nonlinear Circuits Based on a Simplified Volterra Series Model. ISQED 2007: 495-500 - [c210]Rajeshwary Tayade, Savithri Sundareswaran, Jacob A. Abraham:
Small-Delay Defect Detection in the Presence of Process Variations. ISQED 2007: 711-716 - [c209]Ramtilak Vemu, Sankar Gurumurthy, Jacob A. Abraham:
ACCE: Automatic correction of control-flow errors. ITC 2007: 1-10 - [c208]Jacob A. Abraham, Daniel G. Saab:
Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs. VLSI Design 2007: 6 - [c207]Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraham:
Efficient Microprocessor Verification using Antecedent Conditioned Slicing. VLSI Design 2007: 43-49 - [c206]Byoungho Kim, Zhenhai Fu, Jacob A. Abraham:
Transformer-Coupled Loopback Test for Differential Mixed-Signal Specifications. VTS 2007: 291-296 - 2006
- [c205]Qingqi Dou, Jacob A. Abraham:
Jitter decomposition in ring oscillators. ASP-DAC 2006: 285-290 - [c204]Hongjoong Shin, Jiseon Park, Jacob A. Abraham:
A Statistical Digital Equalizer for Loopback-based Linearity Test of Data Converters. ATS 2006: 245-250 - [c203]Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt Jr.:
Automatic insertion of low power annotations in RTL for pipelined microprocessors. DATE 2006: 496-501 - [c202]Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka:
Adaptive Design for Performance-Optimized Robustness. DFT 2006: 3-11 - [c201]Byoungho Kim, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham:
Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance Parameters. ETS 2006: 199-204 - [c200]Vivekananda M. Ve. Andersen, Jacob A. Abraham:
Taming the Complexity of STE-based Design Verification Using Program Slicing. HLDVT 2006: 137-142 - [c199]Ramtilak Vemu, Jacob A. Abraham:
CEDA: Control-flow Error Detection through Assertions. IOLTS 2006: 151-158 - [c198]Qingqi Dou, Jacob A. Abraham:
Jitter Decomposition by Time Lag Correlation. ISQED 2006: 525-530 - [c197]Sankar Gurumurthy, Shobha Vasudevan, Jacob A. Abraham:
Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor. ITC 2006: 1-9 - [c196]Jen-Chieh Ou, Daniel G. Saab, Jacob A. Abraham:
HDL Program Slicing to Reduce Bounded Model Checking Search Overhead. ITC 2006: 1-7 - [c195]Hongjoong Shin, Joonsung Park, Jacob A. Abraham:
Built-in Fault Diagnosis for Tunable Analog Systems Using an Ensemble Method. ITC 2006: 1-10 - [c194]Shobha Vasudevan, Jacob A. Abraham, Vinod Viswanath, Jiajin Tu:
Automatic decomposition for sequential equivalence checking of system level and RTL descriptions. MEMOCODE 2006: 71-80 - [c193]Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri:
Delay Constrained Register Transfer Level Dynamic Power Estimation. PATMOS 2006: 36-46 - [c192]Baker Mohammad, Paul Bassett, Jacob A. Abraham, Adnan Aziz:
Cache Organization for Embeded Processors: CAM-vs-SRAM. SoCC 2006: 299-302 - [c191]Qiang Qiang, Daniel G. Saab, Jacob A. Abraham:
Checking Nested Properties Using Bounded Model Checking and Sequential ATPG. VLSI Design 2006: 225-230 - [c190]Ramyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham:
A Scheme for On-Chip Timing Characterization. VTS 2006: 24-29 - [c189]Hongjoong Shin, Byoungho Kim, Jacob A. Abraham:
Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits. VTS 2006: 412-419 - 2005
- [j65]Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham:
A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor. Formal Methods Syst. Des. 27(1-2): 67-112 (2005) - [c188]Qiang Qiang, Daniel G. Saab, Jacob A. Abraham:
An Emulation Model for Sequential ATPG-Based Bounded Model Checking. FPL 2005: 469-474 - [c187]Qiang Qiang, Chia-Lun Chang, Daniel G. Saab, Jacob A. Abraham:
Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core. ICCD 2005: 461-463 - [c186]Ramyanshu Datta, Sani R. Nassif, Robert K. Montoye, Jacob A. Abraham:
Testing and debugging delay faults in dynamic circuits. ITC 2005: 10 - [c185]S. Guramurthy, Shobha Vasudevan, Jacob A. Abraham:
Automated mapping of pre-computed module-level test sequences to processor instructions. ITC 2005: 10 - 2004
- [j64]Jeongjin Roh, Jacob A. Abraham:
Subband filtering for time and frequency analysis of mixed-signal circuit testing. IEEE Trans. Instrum. Meas. 53(2): 602-611 (2004) - [c184]Jianhua Gan, Shouli Yan, Jacob A. Abraham:
Effects of noise and nonlinearity on the calibration of a non-binary capacitor array in a successive approximation analog-to-digital converter. ASP-DAC 2004: 292-297 - [c183]Ramyanshu Datta, Antony Sebastine, Jacob A. Abraham:
Delay fault testing and silicon debug using scan chains. ETS 2004: 46-51 - [c182]Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Jacob A. Abraham:
On-chip delay measurement for silicon debug. ACM Great Lakes Symposium on VLSI 2004: 145-148 - [c181]Hongjoong Shin, Hak-soo Yu, Jacob A. Abraham:
LFSR-based BIST for analog circuits using slope detection. ACM Great Lakes Symposium on VLSI 2004: 316-321 - [c180]Ji Hwan (Paul) Chun, Hak-soo Yu, Jacob A. Abraham:
An efficient linearity test for on-chip high speed ADC and DAC using loop-back. ACM Great Lakes Symposium on VLSI 2004: 328-331 - [c179]Shobha Vasudevan, Jacob A. Abraham:
Static program transformations for efficient software model checking. IFIP Congress Topical Sessions 2004: 257-281 - [c178]Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung C. Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka:
A low latency and low power dynamic Carry Save Adder. ISCAS (2) 2004: 477-480 - [c177]Jing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham:
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. ITC 2004: 31-37 - [c176]Ashwin Raghunathan, Ji Hwan (Paul) Chun, Jacob A. Abraham, Abhijit Chatterjee:
Quasi-Oscillation Based Test for Improved Prediction of Analog Performance Parameters. ITC 2004: 252-261 - [c175]Alper Sen, Vijay K. Garg, Jacob A. Abraham, Jayanta Bhadra:
Formal Verification of a System-on-Chip Using Computation Slicing. ITC 2004: 810-819 - [c174]Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu:
Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing. ITC 2004: 1118-1127 - [c173]Hak-soo Yu, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham:
Performance Characterization of Mixed-Signal Circuits Using a Ternary Signal Representation. ITC 2004: 1389-1397 - [c172]Jing Zeng, Magdy S. Abadir, G. Vandling, Li-C. Wang, S. Karako, Jacob A. Abraham:
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. MTV 2004: 103-109 - [c171]Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham:
Towards The Complete Elimination of Gate/Switch Level Simulations. VLSI Design 2004: 115- - [c170]Vivekananda M. Vedula, Whitney J. Townsend, Jacob A. Abraham:
Program Slicing for ATPG-Based Property Checking. VLSI Design 2004: 591-596 - [c169]Ashwin Raghunathan, Hongjoong Shin, Jacob A. Abraham, Abhijit Chatterjee:
Prediction of Analog Performance Parameters Using Oscillation Based Test. VTS 2004: 377-382 - [c168]Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham:
Efficient Model Checking of Hardware Using Conditioned Slicing. AVoCS 2004: 279-294 - 2003
- [j63]Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra, Raghuram S. Tupuri:
A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages. J. Electron. Test. 19(2): 149-160 (2003) - [j62]Jeongjin Roh, Jacob A. Abraham:
A comprehensive signature analysis scheme for oscillation-test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10): 1409-1423 (2003) - [j61]Sungbae Hwang, Jacob A. Abraham:
Test data compression and test time reduction using an embedded microprocessor. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 853-862 (2003) - [c167]Hak-soo Yu, Jacob A. Abraham, Sungbae Hwang, Jeongjin Roh:
Efficient loop-back testing of on-chip ADCs and DACs. ASP-DAC 2003: 651-656 - [c166]Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr.:
Quadruple Time Redundancy Adders. DFT 2003: 250-256 - [c165]Jianhua Gan, Shouli Yan, Jacob A. Abraham:
Design and modeling of a 16-bit 1.5MSPS successive approximation ADC with non-binary capacitor array. ACM Great Lakes Symposium on VLSI 2003: 161-164 - [c164]Whitney J. Townsend, Jacob A. Abraham, Parag K. Lala:
On-Line Error Detecting Constant Delay Adder. IOLTS 2003: 17- - [c163]Arun Krishnamachary, Jacob A. Abraham:
Effects of Multi-cycle Sensitization on Delay Tests. VLSI Design 2003: 137-142 - [c162]Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula:
Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines. VLSI Design 2003: 243-248 - [c161]Hak-soo Yu, Sungbae Hwang, Jacob A. Abraham:
DSP-Based Statistical Self Test of On-Chip Converters. VTS 2003: 83-88 - [c160]Kyoil Kim, Jacob A. Abraham, Jayanta Bhadra:
Model Checking of Security Protocols with Pre-configuration. WISA 2003: 1-15 - 2002
- [j60]Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita:
Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table. Formal Methods Syst. Des. 21(1): 95-101 (2002) - [c159]Jason Baumgartner, Andreas Kuehlmann, Jacob A. Abraham:
Property Checking via Structural Analysis. CAV 2002: 151-165 - [c158]Jing Zeng, Magdy S. Abadir, Jacob A. Abraham:
False timing path identification using ATPG techniques and delay-based information. DAC 2002: 562-565 - [c157]Vivekananda M. Vedula, Jacob A. Abraham:
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis. DATE 2002: 730-734 - [c156]Jacob A. Abraham, Arun Krishnamachary, Raghuram S. Tupuri:
A Comprehensive Fault Model for Deep Submicron Digital Circuits. DELTA 2002: 360-364 - [c155]Daniel G. Saab, Fatih Kocan, Jacob A. Abraham:
Massively Parallel/Reconfigurable Emulation Model for the D-algorithm. FPL 2002: 1172-1176 - [c154]Arun Krishnamachary, Jacob A. Abraham:
Test generation for resistive opens in CMOS. ACM Great Lakes Symposium on VLSI 2002: 65-70 - [c153]Sungbae Hwang, Jacob A. Abraham:
Selective-run built-in self-test using an embedded processor. ACM Great Lakes Symposium on VLSI 2002: 124-129 - [c152]Kamalnayan Jayaraman, Vivekananda M. Vedula, Jacob A. Abraham:
Native Mode Functional Self-Test Generation for Systems-on-Chip. ISQED 2002: 280-285 - [c151]Jacob A. Abraham, Vivekananda M. Vedula, Daniel G. Saab:
Verifying Properties Using Sequential ATPG. ITC 2002: 194-202 - [c150]Sungbae Hwang, Jacob A. Abraham:
Optimal BIST Using an Embedded Microprocessor. ITC 2002: 736-745 - [c149]Hak-soo Yu, Jacob A. Abraham:
An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation. ASP-DAC/VLSI Design 2002: 441-446 - [c148]Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra:
Program Slicing for Hierarchical Test Generation. VTS 2002: 237-246 - [c147]Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham:
Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? VTS 2002: 275-280 - 2001
- [j59]Narayanan Krishnamurthy, Magdy S. Abadir, Andrew K. Martin, Jacob A. Abraham:
Design and Development Paradigm for Industrial Formal Verification CAD Tools. IEEE Des. Test Comput. 18(4): 26-35 (2001) - [j58]Suresh Seshadri, Jacob A. Abraham:
Frequency Response Verification of Analog Circuits Using Global Optimization Techniques. J. Electron. Test. 17(5): 395-408 (2001) - [c146]Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir:
Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation. CHARME 2001: 386-402 - [c145]Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham:
Full chip false timing path identification: applications to the PowerPCTM microprocessors. DATE 2001: 514-519 - [c144]Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir:
A language formalism for verification of PowerPCTM custom memories using compositions of abstract specifications. HLDVT 2001: 134-141 - [c143]Arun Krishnamachary, Jacob A. Abraham, Raghuram S. Tupuri:
Timing Verification and Delay Test Generation for Hierarchical Designs. VLSI Design 2001: 157-162 - [c142]Henry Chang, Steve Dollens, Gordon W. Roberts, Charles E. Stroud, Mani Soma, Jacob A. Abraham:
Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them? VTS 2001: 415-416 - [c141]Kyoil Kim, Jacob A. Abraham:
Communication Space Reduction for Formal Verification of Secure Authentication Protocols. WECWIS 2001: 225-227 - 2000
- [j57]Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham:
Validating PowerPC Microprocessor Custom Memories. IEEE Des. Test Comput. 17(4): 61-76 (2000) - [j56]Jian Shen, Jacob A. Abraham:
An RTL Abstraction Technique for Processor Microarchitecture Validation and Test Generation. J. Electron. Test. 16(1-2): 67-81 (2000) - [c140]Nina Saxena, Jacob A. Abraham, Avijit Saha:
Causality based generation of directed test cases. ASP-DAC 2000: 503-508 - [c139]Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham:
A quick and inexpensive method to identify false critical paths using ATPG techniques: an experiment with a PowerPCTM microprocessor. CICC 2000: 71-74 - [c138]Tarachand Pagarani, Fatih Kocan, Daniel G. Saab, Jacob A. Abraham:
Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGA. CICC 2000: 147-150 - [c137]Vivekananda M. Vedula, Jacob A. Abraham:
A novel methodology for hierarchical test generation using functional constraint composition. HLDVT 2000: 9-14 - [c136]Jeongjin Roh, Suresh Seshadri, Jacob A. Abraham:
Verification of Delta-Sigma Converters Using Adaptive Regression Modeling. ICCAD 2000: 182-187 - [c135]Hak-soo Yu, Songjun Lee, Jacob A. Abraham:
An Adder Using Charge Sharing and its Application in DRAMs. ICCD 2000: 311-317 - [c134]Jayanta Batra, Magdy S. Abadir, Jacob A. Abraham:
A Quick and Inexpensive Method to Identify False Critical Paths Using ATPG Techniques: an Experiment with a PowerPC Microprocessor. LATW 2000: 72-76 - [c133]Pradip Bose, Jacob A. Abraham:
Performance and Functional Verification of Microprocessors. VLSI Design 2000: 58-63 - [c132]Raghuram S. Tupuri, Jacob A. Abraham, Daniel G. Saab:
Hierarchical Test Generation for Systems On a Chip. VLSI Design 2000: 198- - [c131]Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham:
Automatic Validation Test Generation Using Extracted Control Models. VLSI Design 2000: 312- - [c130]Jeongjin Roh, Jacob A. Abraham:
A Mixed-Signal BIST Scheme with Time-Division Multiplexing (TDM) Comparator and Counters. VLSI Design 2000: 572- - [c129]Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham:
Validation of PowerPC(tm) Custom Memories using Symbolic Simulation. VTS 2000: 9-14 - [c128]Jeongjin Roh, Jacob A. Abraham:
A Comprehensive TDM Comparator Scheme for Effective Analysis of Oscillation-Based Test. VTS 2000: 143-148
1990 – 1999
- 1999
- [j55]Dinos Moundanos, Jacob A. Abraham:
On Design Validation Using Verification Technology. J. Electron. Test. 15(1-2): 173-189 (1999) - [j54]Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell:
An efficient filter-based approach for combinational verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(11): 1542-1557 (1999) - [j53]Zeyad Alkhalifa, V. S. S. Nair, Narayanan Krishnamurthy, Jacob A. Abraham:
Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection. IEEE Trans. Parallel Distributed Syst. 10(6): 627-641 (1999) - [c127]Jian Shen, Jacob A. Abraham, Dave Baker, Tony Hurson, Martin Kinkade, Gregorio Gervasio, Chen-chau Chu, Guanghui Hu:
Functional Verification of the Equator MAP1000 Microprocessor. DAC 1999: 169-174 - [c126]Raghuram S. Tupuri, Arun Krishnamachary, Jacob A. Abraham:
Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor. DAC 1999: 647-652 - [c125]Richard Raimi, Jacob A. Abraham:
Detecting False Timing Paths: Experiments on PowerPC Microprocessors. DAC 1999: 737-741 - [c124]Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell:
An Efficient Filter-Based Approach for Combinational Verification. DATE 1999: 132-137 - [c123]Chia-Pin R. Liu, Jacob A. Abraham:
Transistor Level Synthesis for Static CMOS Combinational Circuits. Great Lakes Symposium on VLSI 1999: 172-175 - [c122]Dinos Moundanos, Jacob A. Abraham:
Formal Checking of Properties in Complex Systems Using Abstractions. Great Lakes Symposium on VLSI 1999: 280-283 - [c121]Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham:
Improving Witness Search Using Orders on States. ICCD 1999: 452-457 - [c120]Jeongjin Roh, Jacob A. Abraham:
Subband filtering scheme for analog and mixed-signal circuit testing. ITC 1999: 221-229 - [c119]Kyung Tek Lee, Jacob A. Abraham:
Critical path identification and delay tests of dynamic circuits. ITC 1999: 421-430 - [c118]Jacob A. Abraham:
Position Statement: Increasing Test Coverage in a VLSI Design Course. ITC 1999: 1132 - [c117]Rathish Jayabharathi, Manuel A. d'Abreu, Jacob A. Abraham:
FzCRITIC - A Functional Timing Verifier Using a Novel Fuzzy Delay Model. VLSI Design 1999: 232-235 - [c116]Jian Shen, Jacob A. Abraham:
Verification of Processor Microarchitectures. VTS 1999: 189-194 - 1998
- [j52]Jian Shen, Jacob A. Abraham:
Synthesis of Native Mode Self-Test Programs. J. Electron. Test. 13(2): 137-148 (1998) - [j51]Craig M. Chase, Prakash Arunachalam, Jacob A. Abraham:
Memory Distribution: Techniques and Practice for CAD Applications. Parallel Comput. 24(11): 1597-1615 (1998) - [j50]Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Hoskote:
Abstraction Techniques for Validation Coverage Analysis and Test Generation. IEEE Trans. Computers 47(1): 2-14 (1998) - [j49]Naveena Nagi, Abhijit Chatterjee, Heebyung Yoon, Jacob A. Abraham:
Signature analysis for analog and mixed-signal circuit test response compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(6): 540-546 (1998) - [c115]Karl-Erwin Großpietsch, Jacob A. Abraham, Johannes Maier, Hans-Dieter Kochs, Michel Renovell:
From Dependable Computing Systems to Computing for Integrated Dependable Systems? (Panel). FTCS 1998: 296-301 - [c114]Sujit Dey, Jacob A. Abraham, Yervant Zorian:
High-level design validation and test. ICCAD 1998: 3 - [c113]Nina Saxena, Jason Baumgartner, Avijit Saha, Jacob A. Abraham:
To model check or not to model check. ICCD 1998: 314-320 - [c112]Robert W. Sumners, Parminder Chhabra, Jacob A. Abraham:
Lightweight guided random simulation. ISSRE 1998: 185-191 - [c111]Jian Shen, Jacob A. Abraham:
Native mode functional test generation for processors with applications to self test and design validation. ITC 1998: 990-999 - [c110]Kyung Tek Lee, Clay Nordquist, Jacob A. Abraham:
Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits. VTS 1998: 34-41 - [c109]Dinos Moundanos, Jacob A. Abraham:
Using Verification Technology for Validation Coverage Analysis and Test Generation. VTS 1998: 254-259 - 1997
- [j48]Hoon Chang, Jacob A. Abraham:
An Efficient Critical Path Tracing Algorithm for Designing High Performance Vlsi Systems. J. Electron. Test. 11(2): 119-129 (1997) - [j47]Jawahar Jain, James R. Bitner, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell:
Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions. IEEE Trans. Computers 46(11): 1230-1245 (1997) - [j46]Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell, John Moondanos:
Automatic verification of implementations of large circuits against HDL specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(3): 217-228 (1997) - [c108]Jun Yuan, Jian Shen, Jacob A. Abraham, Adnan Aziz:
On Combining Formal and Informal Verification. CAV 1997: 376-387 - [c107]Robert W. Sumners, Jacob A. Abraham:
Hierarchical Specification of System Behavior. HASE 1997: 134-140 - [c106]Raghuram S. Tupuri, Jacob A. Abraham:
A Novel Functional Test Generation Method for Processors Using Commercial ATPG. ITC 1997: 743-752 - [c105]Rajesh Raina, Jacob A. Abraham, A. K. Pujari:
T4: Verification. VLSI Design 1997: 3 - [c104]Raghuram S. Tupuri, Jacob A. Abraham:
A Novel Hierarchical Test Generation Method for Processors. VLSI Design 1997: 540-541 - [c103]Rathish Jayabharathi, Kyung Tek Lee, Jacob A. Abraham:
A Novel Solution for Chip-Level Functional Timing Verification. VTS 1997: 137-142 - [c102]Magdy S. Abadir, Jacob A. Abraham, Hong Hao, C. Hunter, Wayne M. Needham, Ron G. Walther:
Microprocessor Test and Validation: Any New Avenues? VTS 1997: 458-464 - 1996
- [j45]Ashok Balivada, Jin Chen, Jacob A. Abraham:
Analog Testing with Time Response Parameters. IEEE Des. Test Comput. 13(2): 18-25 (1996) - [j44]Ashok Balivada, Hong Zheng, Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham:
A unified approach for fault simulation of linear mixed-signal circuits. J. Electron. Test. 9(1-2): 29-41 (1996) - [j43]V. S. S. Nair, Jacob A. Abraham, Prithviraj Banerjee:
Efficient Techniques for the Analysis of Algorithm-Based Fault Tolerance (ABFT) Schemes. IEEE Trans. Computers 45(4): 499-503 (1996) - [j42]Daniel G. Saab, Youssef Saab, Jacob A. Abraham:
Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(10): 1278-1285 (1996) - [c101]Prakash Arunachalam, Jacob A. Abraham, Manuel A. d'Abreu:
A Hierarchal Approach for Power Reduction in VLSI Chips. Great Lakes Symposium on VLSI 1996: 182- - [c100]Sankaran Karthik, Mark Aitken, Glidden Martin, Srinivasu Pappula, Bob Stettler, Praveen Vishakantaiah, Manuel A. d'Abreu, Jacob A. Abraham:
Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor. ITC 1996: 160-166 - [c99]Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Hoskote:
A Unified Framework for Design Validation and Manufacturing Test. ITC 1996: 875-884 - [c98]Jacob A. Abraham, Gopi Ganapathy:
Practical Test and DFT for Next Generation VLSI. VLSI Design 1996: 3 - [c97]Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell:
On More Efficient Combinational ATPG Using Functional Learning. VLSI Design 1996: 107-110 - [c96]Abhijit Chatterjee, Rathish Jayabharathi, Pankaj Pant, Jacob A. Abraham:
Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages. VTS 1996: 354-361 - [c95]Hong Helena Zheng, Ashok Balivada, Jacob A. Abraham:
A novel test generation approach for parametric faults in linear analog circuits . VTS 1996: 470-475 - 1995
- [j41]Ghani A. Kanawati, Nasser A. Kanawati, Jacob A. Abraham:
FERRARI: A Flexible Software-Based Fault and Error Injection System. IEEE Trans. Computers 44(2): 248-260 (1995) - [c94]Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell:
Automated verification of temporal properties specified as state machines in VHDL. Great Lakes Symposium on VLSI 1995: 100-105 - [c93]Yatin Vasant Hoskote, Dinos Moundanos, Jacob A. Abraham:
Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors. ICCD 1995: 532-537 - [c92]Prakash Arunachalam, Craig M. Chase, Jacob A. Abraham:
A memory distribution mechanism for object oriented applications. SPDP 1995: 354-357 - [c91]Jawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross:
Efficient variable ordering and partial representation algorithm. VLSI Design 1995: 81-86 - [c90]Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham:
Efficient multisine testing of analog circuits. VLSI Design 1995: 234-238 - [c89]Ashok Balivada, Yatin Vasant Hoskote, Jacob A. Abraham:
Verification of transient response of linear analog circuits. VTS 1995: 42-47 - 1994
- [j40]Hoon Chang, Jacob A. Abraham:
An efficient critical path tracing algorithm for sequential circuits. Microprocess. Microprogramming 40(10-12): 913-916 (1994) - [j39]Marc E. Levitt, Kaushik Roy, Jacob A. Abraham:
BiCMOS logic testing. IEEE Trans. Very Large Scale Integr. Syst. 2(2): 241-248 (1994) - [c88]Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther:
Microprocessor Testing: Which Technique is Best? (Panel). DAC 1994: 294 - [c87]James R. Bitner, Jawahar Jain, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell:
Efficient Algorithmic Circuit Verification Using Indexed BDDs. FTCS 1994: 266-275 - [c86]Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell:
Abstraction of data path registers for multilevel verification of large circuits. Great Lakes Symposium on VLSI 1994: 11-14 - [c85]Jawahar Jain, James R. Bitner, Dinos Moundanos, Jacob A. Abraham, Donald S. Fussell:
A new scheme to compute variable orders for binary decision diagrams. Great Lakes Symposium on VLSI 1994: 105-108 - [c84]Daniel G. Saab, Youssef Saab, Jacob A. Abraham:
Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0. ICCAD 1994: 40-43 - [c83]Abhijit Chatterjee, Jacob A. Abraham:
RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults. ICCAD 1994: 340-343 - [c82]Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham:
A Signature Analyzer for Analog and Mixed-signal Circuits. ICCD 1994: 284-287 - [c81]Edwin de Angel, Earl E. Swartzlander Jr., Jacob A. Abraham:
A New Asynchronous Multiplier Using Enable/Disable CMOS Differential Logic. ICCD 1994: 302-305 - [c80]S. Surya, Pradip Bose, Jacob A. Abraham:
Architectural Performance Verification: PowerPCTM Processors. ICCD 1994: 344-347 - [c79]Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell:
Verification of Circuits Described in VHDL through Extraction of Design Intent. VLSI Design 1994: 417-420 - [c78]Thomas Thomas, Praveen Vishakantaiah, Jacob A. Abraham:
Impact of behavioral modifications for testability. VTS 1994: 427-432 - 1993
- [j38]Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham:
Fault simulation of linear analog circuits. J. Electron. Test. 4(4): 345-360 (1993) - [j37]Robert B. Mueller-Thuns, Joseph T. Rahmeh, Jacob A. Abraham, Jalal A. Wehbeh, Daniel G. Saab:
Concurrent Hierarchical and Multilevel Simulation of VLSI Circuits. Simul. 60(2): 79-91 (1993) - [j36]Sankaran Karthik, Jacob A. Abraham:
A Framework for Distributed VLSI Simulation on a Network of Workstations. Simul. 60(2): 95-104 (1993) - [j35]Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham:
VLSI logic and fault simulation on general-purpose parallel computers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(3): 446-460 (1993) - [j34]Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham:
Benchmarking Parallel Processing Platforms: An Applications Perspective. IEEE Trans. Parallel Distributed Syst. 4(8): 947-954 (1993) - [c77]Hoon Chang, Jacob A. Abraham:
VIPER: An Efficient Vigorously Sensitizable Path Extractor. DAC 1993: 112-117 - [c76]Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham:
DRAFTS: Discretized Analog Circuit Fault Simulator. DAC 1993: 509-514 - [c75]Gopi Ganapathy, Jacob A. Abraham:
Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor. DAC 1993: 550-555 - [c74]Praveen Vishakantaiah, Jacob A. Abraham:
Impact of Behavioral Learning on the Compilation of Sequential Circuit Tests. FTCS 1993: 370-379 - [c73]Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham:
Fault-based automatic test generator for linear analog circuits. ICCAD 1993: 88-91 - [c72]Praveen Vishakantaiah, Thomas Thomas, Jacob A. Abraham, Magdy S. Abadir:
AMBIANT: Automatic Generation of Behavioral Modifications for Testability. ICCD 1993: 63-66 - [c71]Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham:
MIXER: Mixed-Signal Fault Simulator. ICCD 1993: 568-571 - [c70]Nasser A. Kanawati, Ghani A. Kanawati, Jacob A. Abraham:
Adding capability checks enhances error detection and isolation in object-based systems. ISSRE 1993: 182-191 - [c69]Praveen Vishakantaiah, Jacob A. Abraham, Daniel G. Saab:
CHEETA: Composition of Hierarchical Sequential Tests Using ATKET. ITC 1993: 606-615 - [c68]Sankaran Karthik, Jacob A. Abraham, Raymond P. Voith:
Optimizations for Behavioral/RTL Simulation. VLSI Design 1993: 311-316 - [c67]Kamal K. Varma, Praveen Vishakantaiah, Jacob A. Abraham:
Generation of testable designs from behavioral descriptions using high level synthesis tools. VTS 1993: 124-130 - 1992
- [j33]Chun-Hung Chen, Jacob A. Abraham:
Generation and evaluation of current and logic tests for switch-level sequential circuits. J. Electron. Test. 3(4): 359-366 (1992) - [j32]Jawahar Jain, Jacob A. Abraham, James R. Bitner, Donald S. Fussell:
Probabilistic Verification of Boolean Functions. Formal Methods Syst. Des. 1(1): 61-115 (1992) - [j31]V. S. S. Nair, Yatin Vasant Hoskote, Jacob A. Abraham:
Probabilistic Evaluation of On-Line Checks in Fault-Tolerant Multiprocessor Systems. IEEE Trans. Computers 41(5): 532-541 (1992) - [j30]Thomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham:
Test compaction for sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(2): 260-267 (1992) - [c66]Praveen Vishakantaiah, Jacob A. Abraham, Magdy S. Abadir:
Automatic Test Knowledge Extraction from VHDL (ATKET). DAC 1992: 273-278 - [c65]Junsheng Long, W. Kent Fuchs, Jacob A. Abraham:
Compiler-Assisted Static Checkpoint Insertion. FTCS 1992: 58-65 - [c64]Ghani A. Kanawati, Nasser A. Kanawati, Jacob A. Abraham:
FERRARI: A Tool for The Validation of System Dependability Properties. FTCS 1992: 336-344 - [c63]Daniel G. Saab, Youssef Saab, Jacob A. Abraham:
CRIS: a test cultivation program for sequential VLSI circuits. ICCAD 1992: 216-219 - [c62]Rabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d'Abreu:
Automatic test generation for linear digital systems with bi-level search using matrix transform methods. ICCAD 1992: 224-228 - [c61]Sankaran Karthik, Jacob A. Abraham:
Distributed VLSI Simulation on a Network of Workstations. ICCD 1992: 508-511 - [c60]John Moondanos, Jacob A. Abraham:
Sequential Redundancy Identification Using Verification Techniques. ITC 1992: 197-205 - [c59]Naveena Nagi, Jacob A. Abraham:
Hierarchical fault modeling for analog and mixed-signal circuits. VTS 1992: 96-101 - 1991
- [j29]Abhijit Chatterjee, Rabindra K. Roy, Jacob A. Abraham, Janak H. Patel:
Efficient testing strategies for bit- and digit-serial arrays used in digital signal processors. Digit. Signal Process. 1(4): 231-244 (1991) - [j28]Abhijit Chatterjee, Jacob A. Abraham:
Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling. J. Electron. Test. 2(4): 351-372 (1991) - [j27]Abhijit Chatterjee, Jacob A. Abraham:
Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model. IEEE Trans. Computers 40(10): 1133-1148 (1991) - [c58]Robert B. Mueller-Thuns, Daniel G. Saab, Jacob A. Abraham:
Parallel switch-level simulation for VLSI. EURO-DAC 1991: 324-328 - [c57]David T. Blaauw, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham:
Functional abstraction of logic gates for switch-level simulation. EURO-DAC 1991: 329-333 - [c56]Jacob A. Abraham:
Design and evaluation of fault tolerance techniques for highly parallel architectures. Great Lakes Symposium on VLSI 1991 - [c55]Jawahar Jain, James R. Bitner, Donald S. Fussell, Jacob A. Abraham:
Probabilistic Design Verification. ICCAD 1991: 468-471 - [c54]Sankaran Karthik, Indira de Souza, Joseph T. Rahmeh, Jacob A. Abraham:
Interlock Schemes for Micropiplines: Application to a Self-Timed Rebound Sorter. ICCD 1991: 393-396 - [c53]Chun-Hung Chen, Jacob A. Abraham:
High Quality Tests for Switch-Level Circuits Using Current and Logic Test Generation Algorithms. ITC 1991: 615-622 - [c52]Gopi Ganapathy, Jacob A. Abraham:
Hardware Acceleration Alone Will Not Make Fault Grading ULSI a Reality. ITC 1991: 848-857 - 1990
- [j26]Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Joseph T. Rahmeh, Jacob A. Abraham:
Hierarchical multi-level fault simulation of large systems. J. Electron. Test. 1(2): 139-149 (1990) - [j25]V. S. S. Nair, Jacob A. Abraham:
Real-Number Codes for Bault-Tolerant Matrix Operations On Processor Arrays. IEEE Trans. Computers 39(4): 426-435 (1990) - [j24]Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Vijay Balasubramanian, Jacob A. Abraham:
Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor. IEEE Trans. Computers 39(9): 1132-1145 (1990) - [j23]Abhijit Chatterjee, Jacob A. Abraham:
The Testability of Generalized Counters Under Multiple Faulty Cells. IEEE Trans. Computers 39(11): 1378-1385 (1990) - [c51]Ramachandra P. Kunda, Jacob A. Abraham, Bharat Deep Rathi, Prakash Narain:
Speed Up of Test Generation Using High-Level Primitives. DAC 1990: 594-599 - [c50]David T. Blaauw, Daniel G. Saab, Junsheng Long, Jacob A. Abraham:
Derivation of signal flow for switch-level simulation. EURO-DAC 1990: 301-305 - [c49]Kaushik Roy, Jacob A. Abraham:
High level test generation using data flow descriptions. EURO-DAC 1990: 480-484 - [c48]Suku Nair, Jacob A. Abraham:
Hierarchical design and analysis of fault-tolerant multiprocessor systems using concurrent error detection. FTCS 1990: 130-137 - [c47]David T. Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham:
SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction. ICCAD 1990: 66-69 - [c46]Chun-Hung Chen, Jacob A. Abraham:
Mixed-Level Sequential Test Generation Using a Nine-Valued Relaxation Algorithm. ICCAD 1990: 230-233 - [c45]David T. Blaauw, Prithviraj Banerjee, Jacob A. Abraham:
Automatic classification of node types in switch-level descriptions. ICCD 1990: 175-178 - [c44]Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Joseph T. Rahmeh, Jacob A. Abraham:
Fault grading of large digital systems. ICCD 1990: 290-293 - [c43]Marc E. Levitt, Kaushik Roy, Jacob A. Abraham:
BiCMOS fault models: is stuck-at adequate? ICCD 1990: 294-297 - [c42]Junsheng Long, W. Kent Fuchs, Jacob A. Abraham:
Forward Recovery Using Checkpointing in Parallel Systems. ICPP (1) 1990: 272-275 - [c41]John C. Chan, Jacob A. Abraham:
A study of faulty signatures using a matrix formulation. ITC 1990: 553-561 - [c40]Robert B. Mueller-Thuns, Daniel G. Saab, Jacob A. Abraham:
Design of a scalable parallel switch-level simulator for VLSI. SC 1990: 615-624
1980 – 1989
- 1989
- [c39]David T. Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh:
Automatic Generation of Behavioral Models from Switch-Level Descriptions. DAC 1989: 179-184 - [c38]Carol V. Gura, Jacob A. Abraham:
Average Interconnection Length and Interconnection Distribution Based on Rent's Rule. DAC 1989: 574-577 - [c37]Kaushik Roy, Jacob A. Abraham:
A Novel Approach to Accurate Timing Verification Using RTL Descriptions. DAC 1989: 638-641 - [c36]Kaushik Roy, Jacob A. Abraham, Kaushik De, Stephen L. Lusky:
Synthesis of delay fault testable combinational logic. ICCAD 1989: 418-421 - [c35]Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham:
Portable parallel logic and fault simulation. ICCAD 1989: 506-509 - [c34]Jacob A. Abraham:
Advances in VLSI-Testing. IFIP Congress 1989: 1013-1018 - [c33]Kurt H. Thearling, Jacob A. Abraham:
An Easily Computed Functional Level Testability Measure. ITC 1989: 381-390 - [c32]Marc E. Levitt, Jacob A. Abraham:
The Economics of Scan Design. ITC 1989: 869-874 - 1988
- [j22]Jing-Yang Jou, Jacob A. Abraham:
Fault-Tolerant FFT Networks. IEEE Trans. Computers 37(5): 548-561 (1988) - [c31]Carol V. Gura, Jacob A. Abraham:
Improved Methods of Simulating RLC Couple and Uncoupled Transmission Lines Based on the Method of Characteristics. DAC 1988: 300-305 - [c30]Patrick A. Duba, Rabindra K. Roy, Jacob A. Abraham, William A. Rogers:
Fault Simulation in a Distributed Environment. DAC 1988: 686-691 - [c29]Suku Nair, Jacob A. Abraham:
General linear codes for fault-tolerant matrix operations on processor arrays. FTCS 1988: 180-185 - [c28]Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Jacob A. Abraham:
An evaluation of system-level fault tolerance on the Intel hypercube multiprocessor. FTCS 1988: 362-367 - [c27]Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Jacob A. Abraham, Joseph T. Rahmeh:
CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits. ICCAD 1988: 246-249 - [c26]Rabindra K. Roy, Thomas M. Niermann, Janak H. Patel, Jacob A. Abraham, Resve A. Saleh:
Compaction of ATPG-generated test sequences for sequential circuits. ICCAD 1988: 382-385 - [c25]Abhijit Chatterjee, Jacob A. Abraham:
NCUBE: an automatic test generation program for iterative logic arrays. ICCAD 1988: 428-431 - [c24]Jing-Yang Jou, Jacob A. Abraham:
Fault-Tolerant Algorithms and Architectures for Real Time Signal Processing. ICPP (1) 1988: 359-362 - [c23]M. J. Marlett, Jacob A. Abraham:
DC_IATP : An Iterative Analog Circuit Test Generation Program for Generating DC Single Pattern Tests. ITC 1988: 839-844 - 1987
- [j21]Jacob A. Abraham, Prithviraj Banerjee, Chien-Yi Chen, W. Kent Fuchs, Sy-Yen Kuo, A. L. Narasimha Reddy:
Fault Tolerance Techniques for Systolic Arrays. Computer 20(7): 65-75 (1987) - [j20]Abhijit Chatterjee, Jacob A. Abraham:
On the C-Testability of Generalized Counters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(5): 713-726 (1987) - [j19]William A. Rogers, John F. Guzolek, Jacob A. Abraham:
Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(5): 848-862 (1987) - [j18]W. Kent Fuchs, Kun-Lung Wu, Jacob A. Abraham:
Comparison and Diagnosis of Large Replicated Files. IEEE Trans. Software Eng. 13(1): 15-22 (1987) - 1986
- [j17]Jacob A. Abraham, W. Kent Fuchs:
Fault and error models for VLSI. Proc. IEEE 74(5): 639-654 (1986) - [j16]Jing-Yang Jou, Jacob A. Abraham:
Fault-tolerant matrix arithmetic and signal processing on highly concurrent computing structures. Proc. IEEE 74(5): 732-741 (1986) - [j15]Prithviraj Banerjee, Jacob A. Abraham:
Bounds on Algorithm-Based Fault Tolerance in Multiple Processor Systems. IEEE Trans. Computers 35(4): 296-306 (1986) - [j14]Timothy C. K. Chou, Jacob A. Abraham:
Distributed Control of Computer Systems. IEEE Trans. Computers 35(6): 564-567 (1986) - [j13]Hsi-Ching Shih, Joseph T. Rahmeh, Jacob A. Abraham:
FAUST: An MOS Fault Simulator with Timing Information. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(4): 557-563 (1986) - [c22]Hsi-Ching Shih, Jacob A. Abraham:
Transistor-level test generation for physical failures in CMOS circuits. DAC 1986: 243-249 - [c21]Chien-Yi Chen, Jacob A. Abraham:
On the Design of Fault-Tolerant Systolic Arrays with Linear Cells. FJCC 1986: 400-409 - [c20]Kien A. Hua, Jacob A. Abraham:
Design of Systems with Concurrent Error Detection Using Software Redundancy. FJCC 1986: 826-835 - [c19]Jacob A. Abraham:
Research in Reliable VLSI Architectures at the University of Illinois. FJCC 1986: 890-893 - [c18]Hongtao P. Chang, William A. Rogers, Jacob A. Abraham:
Structured Functional Level Test Generation Using Binary Decision Diagrams. ITC 1986: 97-104 - [c17]Robert H. Fujii, Jacob A. Abraham:
Approaches to Circuit Level Design for Testability. ITC 1986: 480-483 - [c16]Prithviraj Banerjee, Jacob A. Abraham:
A Probabilistic Model of Algorithm-Based Fault Tolerance in Array Processors for Real-Time Systems. RTSS 1986: 72-78 - [c15]W. Kent Fuchs, Kun-Lung Wu, Jacob A. Abraham:
Low-Cost Comparison and Diagnosis of Large Remotely Located Files. Symposium on Reliability in Distributed Software and Database Systems 1986: 67-73 - 1985
- [j12]Niraj K. Jha, Jacob A. Abraham:
Design of Testable CMOS Logic Circuits Under Arbitrary Delays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(3): 264-269 (1985) - [j11]Prithviraj Banerjee, Jacob A. Abraham:
A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(3): 312-321 (1985) - [c14]William A. Rogers, Jacob A. Abraham:
High level hierarchical fault simulation techniques. ACM Conference on Computer Science 1985: 89-97 - [c13]Peter Y.-T. Hsu, Joseph T. Rahmeh, Edward S. Davidson, Jacob A. Abraham:
TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology. ISCA 1985: 28-35 - [c12]Robert H. Fujii, Jacob A. Abraham:
Self-Test for Microprocessors. ITC 1985: 356-361 - [c11]William A. Rogers, Jacob A. Abraham:
CHIEFS : A Concurrent, Hierarchical and Extensible Fault Simulator. ITC 1985: 710-716 - 1984
- [j10]Prithviraj Banerjee, Jacob A. Abraham:
Characterization and Testing of Physical Failures in MOS Logic Circuits. IEEE Des. Test 1(3): 76-86 (1984) - [j9]Dhananjay Brahme, Jacob A. Abraham:
Functional Testing of Microprocessors. IEEE Trans. Computers 33(6): 475-485 (1984) - [j8]Kuang-Hua Huang, Jacob A. Abraham:
Algorithm-Based Fault Tolerance for Matrix Operations. IEEE Trans. Computers 33(6): 518-528 (1984) - [c10]Prithviraj Banerjee, Jacob A. Abraham:
Fault-Secure Algorithms for Multiple-Processor Systems. ISCA 1984: 279-287 - [c9]Ramaswami Dandapani, Janak H. Patel, Jacob A. Abraham:
Design of Test Pattern Generators for Built-In Test. ITC 1984: 315-319 - 1983
- [j7]Timothy C. K. Chou, Jacob A. Abraham:
Load Redistribution Under Failure in Distributed Systems. IEEE Trans. Computers 32(9): 799-808 (1983) - [c8]Richard L. Norton, Jacob A. Abraham:
Adaptive Interpretation as a Means of Exploiting Complex Instruction Sets. ISCA 1983: 277-282 - [c7]W. Kent Fuchs, Jacob A. Abraham, Kuang-Hua Huang:
Concurrent Error Detection in VLSI Interconnection Networks. ISCA 1983: 309-315 - [c6]Jacob A. Abraham:
Incorporating Test Technology into an Undergraduate Curriculum. ITC 1983: 162 - [c5]Prithviraj Banerjee, Jacob A. Abraham:
Generating Tests for Physical Failures in MOS Logic Circuits. ITC 1983: 554-559 - 1982
- [j6]Timothy C. K. Chou, Jacob A. Abraham:
Load Balancing in Distributed Systems. IEEE Trans. Software Eng. 8(4): 401-412 (1982) - [c4]Pradip Bose, Jacob A. Abraham:
Test generation for programmable logic arrays. DAC 1982: 574-580 - [c3]Kuang-Hua Huang, Jacob A. Abraham:
Efficient parallel algorithms for processor arrays. ICPP 1982: 268-279 - [c2]Richard L. Norton, Jacob A. Abraham:
Using write back cache to improve performance of multi-user multiprocessors. ICPP 1982: 326-331 - 1981
- [j5]Jacob A. Abraham, Daniel Gajski:
Design of Testable Structures Defined by Simple Loops. IEEE Trans. Computers 30(11): 875-884 (1981) - [c1]Jacob A. Abraham:
Functional Level Test Generation for Complex Digital Systems. ITC 1981: 461-462 - 1980
- [j4]Satish M. Thatte, Jacob A. Abraham:
Test Generation for Microprocessors. IEEE Trans. Computers 29(6): 429-441 (1980)
1970 – 1979
- 1978
- [j3]Ravindra Nair, Satish M. Thatte, Jacob A. Abraham:
Efficient Algorithms for Testing Semiconductor Random-Access Memories. IEEE Trans. Computers 27(6): 572-576 (1978) - 1975
- [j2]Jacob A. Abraham:
A Combinatorial Solution to the Reliability of Interwoven Redundant Logic Networks. IEEE Trans. Computers 24(5): 578-584 (1975) - 1974
- [j1]Jacob A. Abraham, Daniel P. Siewiorek:
An Algorithm for the Accurate Reliability Evaluation of Triple Modular Redundancy Networks. IEEE Trans. Computers 23(7): 682-692 (1974)
Coauthor Index
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Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-11-11 21:28 CET by the dblp team
all metadata released as open data under CC0 1.0 license
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since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
