Spatially distributed 3D circuit models - Michael W. Beattie; Hui Zheng; Anirudh Devgan; Byron Krauter (Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, 2005)

Parasitics extraction with multipole refinement - Michael W. Beattie; Lawrence T. Pileggi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

On-chip induction modeling: basics and advanced methods - Michael W. Beattie; Lawrence T. Pileggi (IEEE Trans. Very Large Scale Integr. Syst., 2002)

On the efficacy of simplified 2D on-chip inductance models - Tao Lin; Michael W. Beattie; Lawrence T. Pileggi (Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, 2002)

Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses - Hui Zheng; Lawrence T. Pileggi; Michael W. Beattie; Byron Krauter (2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, 2002)

On-Chip Inductance Models: 3D or Not 3D? - Tao Lin; Michael W. Beattie; Lawrence T. Pileggi (2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, 2002)

Equipotential shells for efficient inductance extraction - Michael W. Beattie; Byron Krauter; Lale Alatan; Lawrence T. Pileggi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Inductance 101: Modeling and Extraction - Michael W. Beattie; Lawrence T. Pileggi (Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001, 2001)

Modeling Magnetic Coupling for On-Chip Interconnect - Michael W. Beattie; Lawrence T. Pileggi (Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001, 2001)

Efficient inductance extraction via windowing - Michael W. Beattie; Lawrence T. Pileggi (Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2001, Munich, Germany, March 12-16, 2001, 2001)

Hierarchical Interconnect Circuit Models - Michael W. Beattie; Satrajit Gupta; Lawrence T. Pileggi (Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000, San Jose, California, USA, November 5-9, 2000, 2000)

Error bounds for capacitance extraction via window techniques - Michael W. Beattie; Lawrence T. Pileggi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

IC Analyses Including Extracted Inductance Models - Michael W. Beattie; Lawrence T. Pileggi (Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999, 1999)

Electromagnetic parasitic extraction via a multipole method with hierarchical refinement - Michael W. Beattie; Lawrence T. Pileggi (Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, 1999)

Bounds for BEM Capacitance Extraction - Michael W. Beattie; Lawrence T. Pileggi (Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997, 1997)