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ORCIDJulien Lamoureux
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2010 – 2019
- 2010
[c11]Julien Lamoureux, Scott Miller, Mihai Sima:
Fine-grained vs. coarse-grained shift-and-add arithmetic in FPGAs (abstract only). FPGA 2010: 290
2000 – 2009
- 2009
- [c10]Julien Lamoureux, Tony Field, Wayne Luk:
Accelerating a Virtual Ecology Model with FPGAs. ASAP 2009: 67-74 - 2008
- [j4]Chi Wai Yu, Julien Lamoureux, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk:
The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units. Int. J. Reconfigurable Comput. 2008: 736203:1-736203:10 (2008) - [j3]Julien Lamoureux, Steven J. E. Wilton:
On the trade-off between power and flexibility of FPGA clock networks. ACM Trans. Reconfigurable Technol. Syst. 1(3): 13:1-13:33 (2008) - [j2]Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton:
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. IEEE Trans. Very Large Scale Integr. Syst. 16(11): 1521-1534 (2008) - [c9]Julien Lamoureux, Wayne Luk:
An Overview of Low-Power Techniques for Field-Programmable Gate Arrays. AHS 2008: 338-345 - 2007
- [c8]Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton:
GlitchLess: an active glitch minimization technique for FPGAs. FPGA 2007: 156-165 - [c7]Julien Lamoureux, Steven J. E. Wilton:
Clock-Aware Placement for FPGAs. FPL 2007: 124-131 - 2006
- [c6]Julien Lamoureux, Steven J. E. Wilton:
FPGA clock network architecture: flexibility vs. area and power. FPGA 2006: 101-108 - [c5]Julien Lamoureux, Steven J. E. Wilton:
Activity Estimation for Field-Programmable Gate Arrays. FPL 2006: 1-8 - [c4]Julien Lamoureux, Steven J. E. Wilton:
Architecture and CAD for FPGA Clock Networks. FPL 2006: 1-2 - 2005
- [j1]Julien Lamoureux, Steven J. E. Wilton:
On the Interaction between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays. J. Low Power Electron. 1(2): 119-132 (2005) - 2004
- [c3]Steven J. E. Wilton, Christopher W. Jones, Julien Lamoureux:
An embedded flexible content-addressable memory core for inclusion in a Field-Programmable Gate Array. ISCAS (2) 2004: 885-888 - 2003
- [c2]Julien Lamoureux, Steven J. E. Wilton:
On the Interaction Between Power-Aware FPGA CAD Algorithms. ICCAD 2003: 701-708 - 2001
- [c1]Natalia Kazakova, Raymond J. Sung, Nelson G. Durdle, Martin Margala
, Julien Lamoureux:
Fast and low-power inner product processor. ISCAS (4) 2001: 646-649
Coauthor Index
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