The Path to Successful Wafer-Scale Integration: The Cerebras Story. - Lauterbach, Gary (IEEE Micro, 2021)

A novel system architecture for web scale applications using lightweight CPUs and virtualized I/O. - Sudan, Kshitij; Balakrishnan, Saisanthosh; Lie, Sean; Xu, Min; Mallick, Dhiraj; Lauterbach, Gary; Balasubramonian, Rajeev (2013)

SeaMicro SM10000-64 server: Building datacenter servers using cell phone chips. - Dhodapkar, Ashutosh; Lauterbach, Gary; Lie, Sean; Mallick, Dhiraj; Bauman, Jim; Kanthadai, Sundar; Kuzuhara, Toru; Shen, Gene; Xu, Min; Zhang, Chris (2011)

Challenges in Building a Flat-Bandwidth Memory Hierarchy for a Large-Scale Computer with Proximity Communication. - Drost, Robert J.; Forrest, Craig; Guenin, Bruce; Ho, Ron; Krishnamoorthy, Ashok V.; Cohen, Danny; Cunningham, John E.; Tourancheau, Bernard; Zingher, Arthur; Chow, Alex; Lauterbach, Gary; Sutherland, Ivan E. (2005)

Robust Highly-Connected Direct Interconnection Network Topologies. - Sharapov, Ilya; Lauterbach, Gary; Crago, Stephen P. (2003)

A third-generation SPARC V9 64-b microprocessor. - Heald, Raymond A.; Aingaran, Kathirgamar; Amir, Chaim; Ang, Michael; Boland, Michael; Dixit, Pankaj; Gouldsberry, Gary; Greenley, Dale; Grinberg, Joel; Hart, Jason M.; Horel, Tim; Hsu, Wen-Jay; et al. (IEEE J. Solid State Circuits, 2000)

Vying for the Lead in High-Performance Processors (Interview). - Lauterbach, Gary (Computer, 1999)

UltraSPARC-III: designing third-generation 64-bit performance. - Horel, Tim; Lauterbach, Gary (IEEE Micro, 1999)

64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency. - Heald, Raymond A.; Shin, Ken; Reddy, Vinita; Kao, I-Feng; Khan, Masood; Lynch, William L.; Lauterbach, Gary; Petolino, Joe (IEEE J. Solid State Circuits, 1998)

Low Load Latency Through Sum-Addressed Memory (SAM). - Lynch, William L.; Lauterbach, Gary; Chamdani, Joseph I. (1998)

Accelerating Architectural Simulation by Parallel Execution of Trace Samples. - Lauterbach, Gary (1994)