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ORCIDToshihiro Hanawa
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2020 – today
- 2024
[c57]Shinji Sumimoto
, Toshihiro Hanawa, Kengo Nakajima:
MPI-Adapter2: An Automatic ABI Translation Library Builder for MPI Application Binary Portability. HPC Asia Workshops 2024: 63-68- [c56]Masatoshi Kawai, Akihiro Ida, Toshihiro Hanawa, Tetsuya Hoshino:
Optimize Efficiency of Utilizing Systems by Dynamic Core Binding. HPC Asia Workshops 2024: 77-82 - 2023
- [c55]Masatoshi Kawai, Akihiro Ida, Toshihiro Hanawa, Kengo Nakajima:
Dynamic Core Binding for Load Balancing of Applications Parallelized with MPI/OpenMP. ICCS (3) 2023: 378-394 - [e3]Hiroyuki Takizawa, Hong Shen, Toshihiro Hanawa, Jong Hyuk Park, Hui Tian, Ryusuke Egawa:
Parallel and Distributed Computing, Applications and Technologies - 23rd International Conference, PDCAT 2022, Sendai, Japan, December 7-9, 2022, Proceedings. Lecture Notes in Computer Science 13798, Springer 2023, ISBN 978-3-031-29926-1 [contents] - 2022
- [c54]Tetsuya Hoshino, Akihiro Ida, Toshihiro Hanawa:
Optimizations of H-matrix-vector Multiplication for Modern Multi-core Processors. CLUSTER 2022: 462-472 - [c53]Toyotaro Suzumura, Akiyoshi Sugiki, Hiroyuki Takizawa, Akira Imakura, Hiroshi Nakamura, Kenjiro Taura, Tomohiro Kudoh, Toshihiro Hanawa, Yuji Sekiya, Hill Hiroki Kobayashi, Yohei Kuga, Ryo Nakamura, Renhe Jiang, Junya Kawase, Masatoshi Hanai, Hiroshi Miyazaki, Tsutomu Ishizaki, Daisuké Shimotoku, Daisuke Miyamoto, Kento Aida, Atsuko Takefusa, Takashi Kurimoto, Koji Sasayama, Naoya Kitagawa, Ikki Fujiwara, Yusuke Tanimura, Takayuki Aoki, Toshio Endo, Satoshi Ohshima, Keiichiro Fukazawa, Susumu Date, Toshihiro Uchibayashi:
mdx: A Cloud Platform for Supporting Data Science and Cross-Disciplinary Research Collaborations. DASC/PiCom/CBDCom/CyberSciTech 2022: 1-7 - [c52]Shinji Sumimoto, Toshihiro Hanawa, Kengo Nakajima:
A Process Management Runtime with Dynamic Reconfiguration. HPC Asia Workshops 2022: 10-18 - [c51]Tadayoshi Hara, Toshihiro Hanawa:
Offloading Transprecision Calculation Using FPGA. HPC Asia Workshops 2022: 19-28 - [c50]Shinji Sumimoto, Takashi Arakawa, Yoshio Sakaguchi, Hiroya Matsuba, Hisashi Yashiro, Toshihiro Hanawa, Kengo Nakajima:
A System-Wide Communication to Couple Multiple MPI Programs for Heterogeneous Computing. PDCAT 2022: 314-327 - [i2]Toyotaro Suzumura, Akiyoshi Sugiki, Hiroyuki Takizawa, Akira Imakura, Hiroshi Nakamura, Kenjiro Taura, Tomohiro Kudoh, Toshihiro Hanawa, Yuji Sekiya, Hill Hiroki Kobayashi, Shin Matsushima, Yohei Kuga, Ryo Nakamura, Renhe Jiang, Junya Kawase, Masatoshi Hanai, Hiroshi Miyazaki, Tsutomu Ishizaki, Daisuké Shimotoku, Daisuke Miyamoto, Kento Aida, Atsuko Takefusa, Takashi Kurimoto, Koji Sasayama, Naoya Kitagawa, Ikki Fujiwara, Yusuke Tanimura, Takayuki Aoki, Toshio Endo, Satoshi Ohshima, Keiichiro Fukazawa, Susumu Date, Toshihiro Uchibayashi:
mdx: A Cloud Platform for Supporting Data Science and Cross-Disciplinary Research Collaborations. CoRR abs/2203.14188 (2022) - 2021
- [c49]Masahiro Tanaka, Kenjiro Taura, Toshihiro Hanawa, Kentaro Torisawa:
Automatic Graph Partitioning for Very Large-scale Deep Learning. IPDPS 2021: 1004-1013 - [i1]Masahiro Tanaka, Kenjiro Taura, Toshihiro Hanawa, Kentaro Torisawa:
Automatic Graph Partitioning for Very Large-scale Deep Learning. CoRR abs/2103.16063 (2021) - 2020
- [j7]Yukihiro Nomura, Issei Sato, Toshihiro Hanawa, Shouhei Hanaoka, Takahiro Nakao, Tomomi Takenaga, Tetsuya Hoshino, Yuji Sekiya, Soichiro Miki, Takeharu Yoshikawa, Naoto Hayashi, Osamu Abe:
Development of training environment for deep learning with medical images on supercomputer system based on asynchronous parallel Bayesian optimization. J. Supercomput. 76(9): 7315-7332 (2020) - [c48]Jorji Nonaka, Toshihiro Hanawa, Fumiyoshi Shoji:
Analysis of Cooling Water Temperature Impact on Computing Performance and Energy Consumption. CLUSTER 2020: 169-175 - [c47]Tadahiko Murata, Susumu Date, Yusuke Goto, Toshihiro Hanawa, Takuya Harada, Manabu Ichikawa, Lee Hao, Masaharu Munetomo, Akiyoshi Sugiki:
Distribution System for Japanese Synthetic Population Data with Protection Level. ICMLC 2020: 187-193 - [c46]Eishi Arima, Toshihiro Hanawa, Carsten Trinitis, Martin Schulz:
Footprint-Aware Power Capping for Hybrid Memory Based Systems. ISC 2020: 347-369
2010 – 2019
- 2019
- [j6]Masahiro Nakao, Tetsuya Odajima, Hitoshi Murai, Akihiro Tabuchi, Norihisa Fujita, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato:
Evaluation of XcalableACC with tightly coupled accelerators/InfiniBand hybrid communication on accelerated cluster. Int. J. High Perform. Comput. Appl. 33(5) (2019) - 2018
- [c45]Tetsuya Hoshino, Akihiro Ida, Toshihiro Hanawa, Kengo Nakajima:
Load-Balancing-Aware Parallel Algorithms of H-Matrices with Adaptive Cross Approximation for GPUs. CLUSTER 2018: 35-45 - [c44]Masashi Horikoshi, Larry Meadows, Tom Elken, Pradeep Sivakumar, Edward Mascarenhas, James Erwin, Dmitry Durnov, Alexander Sannikov, Toshihiro Hanawa, Taisuke Boku:
Scaling collectives on large clusters using Intel(R) architecture processors and fabric. HPC Asia Workshops 2018: 59-62 - [c43]Tetsuya Hoshino, Akihiro Ida, Toshihiro Hanawa, Kengo Nakajima:
Design of Parallel BEM Analyses Framework for SIMD Processors. ICCS (1) 2018: 601-613 - [c42]Sang-Yuep Kim, Takahiro Suzuki, Junichi Kani, Akihiro Otaka, Toshihiro Hanawa:
Coherent Receiver DSP Implemented on a General-Purpose Server for Full Software-Defined Optical Access. OFC 2018: 1-3 - [c41]Takahiro Suzuki, Sang-Yuep Kim, Junichi Kani, Akihiro Otaka, Toshihiro Hanawa:
10-Gbps Real-time Burst-Frame Synchronization Using Dual-Stage Detection for Full-Software Optical Access Systems. OFC 2018: 1-3 - [e2]Toshio Endo, Mitsuo Yokokawa, Toshihiro Hanawa, Osamu Tatebe:
The Proceedings of Workshops of HPC Asia 2018, Chiyoda, Tokyo, Japan, January 31, 2018. ACM 2018, ISBN 978-1-4503-6347-1 [contents] - 2017
- [c40]Takahiro Kaneda, Ryotaro Sakai, Naoki Nishikawa, Toshihiro Hanawa, Chiharu Tsuruta, Hideharu Amano:
Performance Evaluation of PEACH3: Field-Programmable Gate Array Switch for Tightly Coupled Accelerators. HEART 2017: 9:1-9:6 - [c39]Kengo Nakajima, Toshihiro Hanawa:
Communication-Computation Overlapping with Dynamic Loop Scheduling for Preconditioned Parallel Iterative Solvers on Multicore and Manycore Clusters. ICPP Workshops 2017: 210-219 - 2016
- [c38]Satoshi Matsuoka, Hideharu Amano, Kengo Nakajima, Koji Inoue, Tomohiro Kudoh, Naoya Maruyama, Kenjiro Taura, Takeshi Iwashita, Takahiro Katagiri, Toshihiro Hanawa, Toshio Endo:
From FLOPS to BYTES: disruptive change in high-performance computing towards the post-moore era. Conf. Computing Frontiers 2016: 274-281 - [c37]Kazuya Matsumoto, Norihisa Fujita, Toshihiro Hanawa, Taisuke Boku:
Implementation and Evaluation of NAS Parallel CG Benchmark on GPU Cluster with Proprietary Interconnect TCA. VECPAR 2016: 135-145 - 2015
- [c36]Takahiro Suzuki, Sang-Yuep Kim, Junichi Kani, Ken-Ichi Suzuki, Akihiro Otaka, Toshihiro Hanawa:
Parallelization of cipher algorithm on CPU/GPU for real-time software-defined access network. APSIPA 2015: 484-487 - [c35]Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Hideharu Amano, Hitoshi Murai, Masayuki Umemura, Mitsuhisa Sato:
Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing. ARC 2015: 463-474 - [c34]Toshihiro Hanawa, Hisafumi Fujii, Norihisa Fujita, Tetsuya Odajima, Kazuya Matsumoto, Yuetsu Kodama, Taisuke Boku:
Improving Strong-Scaling on GPU Cluster Based on Tightly Coupled Accelerators Architecture. CLUSTER 2015: 88-91 - [c33]Tetsuya Odajima, Taisuke Boku, Toshihiro Hanawa, Hitoshi Murai, Masahiro Nakao, Akihiro Tabuchi, Mitsuhisa Sato:
Hybrid Communication with TCA and InfiniBand on a Parallel Programming Language XcalableACC for GPU Clusters. CLUSTER 2015: 627-634 - [c32]Toshihiro Hanawa, Hisafumi Fujii, Norihisa Fujita, Tetsuya Odajima, Kazuya Matsumoto, Taisuke Boku:
Evaluation of FFT for GPU Cluster Using Tightly Coupled Accelerators Architecture. CLUSTER 2015: 635-641 - [c31]Takuya Kuhara, Chiharu Tsuruta, Toshihiro Hanawa, Hideharu Amano:
Reduction calculator in an FPGA based switching Hub for high performance clusters. FPL 2015: 1-4 - [c30]Kazuya Matsumoto, Toshihiro Hanawa, Yuetsu Kodama, Hisafumi Fujii, Taisuke Boku:
Implementation of CG Method on GPU Cluster with Proprietary Interconnect TCA for GPU Direct Communication. IPDPS Workshops 2015: 647-655 - 2014
- [j5]Yuetsu Kodama, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato:
PEACH2: An FPGA-based PCIe network device for Tightly Coupled Accelerators. SIGARCH Comput. Archit. News 42(4): 3-8 (2014) - [c29]Norihisa Fujita, Hisafumi Fujii, Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Yoshinobu Kuramashi, Mike Clark:
QCD Library for GPU Cluster with Proprietary Interconnect for GPU Direct Communication. Euro-Par Workshops (1) 2014: 251-262 - [c28]Takuya Kuhara, Takahiro Kaneda, Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Hideharu Amano:
A Preliminarily Evaluation of PEACH3: A Switching Hub for Tightly Coupled Accelerators. CANDAR 2014: 377-381 - [c27]Masahiro Nakao, Hitoshi Murai, Takenori Shimosaka, Akihiro Tabuchi, Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Mitsuhisa Sato:
XcalableACC: extension of XcalableMP PGAS language using OpenACC for accelerator clusters. WACCPD@SC 2014: 27-36 - 2013
- [c26]Takaaki Miyajima, Takuya Kuhara, Toshihiro Hanawa, Hideharu Amano, Taisuke Boku:
Task level pipelining with PEACH2: An FPGA switching fabric for high performance computing. FPT 2013: 466-469 - [c25]Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Mitsuhisa Sato:
Interconnection Network for Tightly Coupled Accelerators Architecture. Hot Interconnects 2013: 79-82 - [c24]Tetsuya Odajima, Taisuke Boku, Mitsuhisa Sato, Toshihiro Hanawa, Yuetsu Kodama, Raymond Namyst, Samuel Thibault, Olivier Aumage:
Adaptive Task Size Control on High Level Programming for GPU/CPU Work Sharing. ICA3PP (2) 2013: 59-68 - [c23]Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Mitsuhisa Sato:
Tightly Coupled Accelerators Architecture for Minimizing Communication Latency among Accelerators. IPDPS Workshops 2013: 1030-1039 - 2012
- [c22]Hajime Fujita, Yutaka Matsuno, Toshihiro Hanawa, Mitsuhisa Sato, Shinpei Kato, Yutaka Ishikawa:
DS-Bench Toolset: Tools for dependability benchmarking with simulation and assurance. DSN 2012: 1-8 - [c21]Tetsuya Odajima, Taisuke Boku, Toshihiro Hanawa, Jinpil Lee, Mitsuhisa Sato:
GPU/CPU Work Sharing with Parallel Language XcalableMP-dev for Parallelized Accelerated Computing. ICPP Workshops 2012: 97-106 - 2011
- [j4]Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Toshihiro Hanawa, Shin'ichi Miura, Taisuke Boku:
Peach: A Multicore Communication System on Chip with PCI Express. IEEE Micro 31(6): 39-50 (2011) - [c20]Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato:
An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller. COOL Chips 2011: 1-3 - [c19]Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato:
XMCAPI: Inter-core Communication Interface on Multi-chip Embedded Systems. EUC 2011: 397-402 - [c18]Toshihiro Hanawa, Taisuke Boku, Shin'ichi Miura, Mitsuhisa Sato, Kazutami Arimoto:
PEARL and PEACH: A Novel PCI Express Direct Link and Its Implementation. IPDPS Workshops 2011: 871-879 - [c17]Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Yasushi Hayakawa, Takeshi Oshita, Satoshi Kaneko, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato:
An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs. ISSCC 2011: 266-268 - 2010
- [c16]Takayuki Banzai, Hitoshi Koizumi, Ryo Kanbayashi, Takayuki Imada, Toshihiro Hanawa, Mitsuhisa Sato:
D-Cloud: Design of a Software Testing Environment for Reliable Distributed Systems Using Cloud Computing Technology. CCGRID 2010: 631-636 - [c15]Toshihiro Hanawa, Taisuke Boku, Shin'ichi Miura, Mitsuhisa Sato, Kazutami Arimoto:
PEARL: Power-Aware, Dependable, and High-Performance Communication Link Using PCI Express. GreenCom/CPSCom 2010: 284-291 - [c14]Toshihiro Hanawa, Takayuki Banzai, Hitoshi Koizumi, Ryo Kanbayashi, Takayuki Imada, Mitsuhisa Sato:
Large-Scale Software Testing Environment Using Cloud Computing Technology for Dependable Parallel and Distributed Systems. ICST Workshops 2010: 428-433 - [c13]Toshihiro Hanawa, Hitoshi Koizumi, Takayuki Banzai, Mitsuhisa Sato, Shin'ichi Miura, Tadatoshi Ishii, Hidehisa Takamizawa:
Customizing Virtual Machine with Fault Injector by Integrating with SpecC Device Model for a Software Testing Environment D-Cloud. PRDC 2010: 47-54 - [e1]Mitsuhisa Sato, Toshihiro Hanawa, Matthias S. Müller, Barbara M. Chapman, Bronis R. de Supinski:
Beyond Loop Level Parallelism in OpenMP: Accelerators, Tasking and More, 6th Internationan Workshop on OpenMP, IWOMP 2010, Tsukuba, Japan, June 14-16, 2010, Proceedings. Lecture Notes in Computer Science 6132, Springer 2010, ISBN 978-3-642-13216-2 [contents]
2000 – 2009
- 2009
- [c12]Taiga Yonemoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato:
Flexible Multi-link Ethernet Binding System for PC Clusters with Asymmetric Topology. ICPADS 2009: 49-56 - [c11]Shin'ichi Miura, Toshihiro Hanawa, Taiga Yonemoto, Taisuke Boku, Mitsuhisa Sato:
RI2N/DRV: Multi-link ethernet for high-bandwidth and fault-tolerant network on PC clusters. IPDPS 2009: 1-7 - [c10]Yutaka Ishikawa, Hajime Fujita, Toshiyuki Maeda, Motohiko Matsuda, Midori Sugaya, Mitsuhisa Sato, Toshihiro Hanawa, Shin'ichi Miura, Taisuke Boku, Yuki Kinebuchi, Lei Sun, Tatsuo Nakajima, Jin Nakazawa, Hideyuki Tokuda:
Towards an Open Dependable Operating System. ISORC 2009: 20-27 - [c9]Toshihiro Hanawa, Mitsuhisa Sato, Jinpil Lee, Takayuki Imada, Hideaki Kimura, Taisuke Boku:
Evaluation of Multicore Processors for Embedded Systems by Parallel Benchmark Program Using OpenMP. IWOMP 2009: 15-27 - 2008
- [c8]Shin'ichi Miura, Takayuki Okamoto, Taisuke Boku, Toshihiro Hanawa, Mitsuhisa Sato:
RI2N: High-bandwidth and fault-tolerant network with multi-link Ethernet for PC clusters. CLUSTER 2008: 274-279 - [c7]Shin'ichi Miura, Taisuke Boku, Takayuki Okamoto, Toshihiro Hanawa:
A dynamic routing control system for high-performance PC cluster with multi-path Ethernet connection. IPDPS 2008: 1-8 - 2005
- [j3]Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Yasuki Tanabe, Toshihiro Hanawa, Hideharu Amano:
The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism). Parallel Comput. 31(3-4): 352-370 (2005) - [c6]Toshihiro Hanawa, Toshiya Minai, Yasuki Tanabe, Hideharu Amano:
Implementation of ISIS-SimpleScalar. PDPTA 2005: 117-123 - 2003
- [c5]Yasuki Tanabe, Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Toshihiro Hanawa, Hideharu Amano:
Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism. PDPTA 2003: 1148-1154
1990 – 1999
- 1999
- [j2]Junji Yamamoto, Takashi Fujiwara, T. Komeda, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano:
Performance evaluation of SNAIL: A multiprocessor based on the simple serial synchronized multistage interconnection network architecture. Parallel Comput. 25(9): 1081-1103 (1999) - 1998
- [c4]Takashi Midorikawa, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano:
The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip. ASP-DAC 1998: 337-338 - 1997
- [c3]Akira Funahashi, Toshihiro Hanawa, Hideharu Amano, Tomohiro Kudoh:
Adaptive Routing on the Recursive Diagonal Torus. ISHPC 1997: 171-182 - 1996
- [c2]Toshihiro Hanawa, Takashi Fujiwara, Hideharu Amano:
Hot spot contention and message combining in the simple serial synchronized multistage interconnection network. SPDP 1996: 298-305 - 1995
- [j1]Kalidou Gaye, Toshihiro Hanawa, Hideharu Amano:
An analysis of the hot spot contention and message combining on the simple serial synchronized-multistage interconnection network. Syst. Comput. Jpn. 26(9): 1-12 (1995) - 1994
- [c1]Toshihiro Hanawa, Hideharu Amano, Yoshifumi Fujikawa:
Multistage Interconnection Networks with Multiple Outlets. ICPP (1) 1994: 1-8
Coauthor Index
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