Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool - Levent Aksoy; Cristiano Lazzari; Eduardo Costa; Paulo F. Flores; José Monteiro (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Evaluating the scalability of test buses - Alexandre M. Amory; Matheus T. Moreira; Ney Laert Vilar Calazans; Fernando Gehm Moraes; Cristiano Lazzari; Marcelo Soares Lubaszewski (2013 International Symposium on System on Chip, ISSoC 2013, Tampere, Finland, October 23-24, 2013, 2013)

High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications - Levent Aksoy; Cristiano Lazzari; Eduardo Costa; Paulo F. Flores; José Monteiro (Integr., 2012)

Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays - Cristiano Lazzari; Jorge R. Fernandes; Paulo F. Flores; José Monteiro (J. Low Power Electron., 2011)

A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms - Alexandre M. Amory; Cristiano Lazzari; Marcelo Lubaszewski; Fernando Gehm Moraes (J. Parallel Distributed Comput., 2011)

Efficient shift-adds design of digit-serial multiple constant multiplications - Levent Aksoy; Cristiano Lazzari; Eduardo Costa; Paulo F. Flores; José Monteiro (Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011, 2011)

Optimization of area in digit-serial Multiple Constant Multiplications at gate-level - Levent Aksoy; Cristiano Lazzari; Eduardo Costa; Paulo F. Flores; José Monteiro (International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil, 2011)

Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCs - Alexandre M. Amory; Cristiano Lazzari; Marcelo Lubaszewski; Fernando Gehm Moraes (24th Symposium on Integrated Circuits and Systems Design, SBCCI '11, João Pessoa, Brazil, August 30 - September 2, 2011, 2011)

A new quaternary FPGA based on a voltage-mode multi-valued circuit - Cristiano Lazzari; Paulo F. Flores; José Monteiro; Luigi Carro (Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010, 2010)

A Cost-Effective Technique for Mapping BLUTs to QLUTs in FPGAs - Marcus Ritt; Carlos Arthur Lang Lisbôa; Luigi Carro; Cristiano Lazzari (International Conference on Field Programmable Logic and Applications, FPL 2010, August 31 2010 - September 2, 2010, Milano, Italy, 2010)

Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach - Sidinei Ghissoni; Eduardo Costa; Cristiano Lazzari; José Monteiro; Levent Aksoy; Ricardo Reis (17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece, 12-15 December, 2010, 2010)

Voltage-mode quaternary FPGAs: An evaluation of interconnections - Cristiano Lazzari; Paulo F. Flores; José Monteiro; Luigi Carro (International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, 2010)

An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs - Cristiano Lazzari; Jorge R. Fernandes; Paulo F. Flores; José Monteiro (Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers, 2010)

CMOS voltage-mode quaternary look-up tables for multi-valued FPGAs - Ricardo C. Goncalves da Silva; Cristiano Lazzari; Henri Boudinov; Luigi Carro (Microelectron. J., 2009)

An automated design methodology for layout generation targeting power leakage minimization - Cristiano Lazzari; Adriel Ziesemer; Ricardo Reis (16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009, Yasmine Hammamet, Tunisia, 13-19 December, 2009, 2009)

A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis - Cristiano Lazzari; Ricardo A. L. Reis; Lorena Anghel (J. Electron. Test., 2007)

An Educational Tool for Design Automation of CMOS Cells - Adriel Ziesemer; Cristiano Lazzari; Ricardo Reis (IEEE International Conference on Microelectronic Systems Education, MSE '07, San Diego, CA, USA, June 3-4, 2007, 2007)

Transistor level automatic layout generator for non-complementary CMOS cells - Adriel Ziesemer; Cristiano Lazzari (IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, 2007)

Efficient timing closure with a transistor level design flow - Cristiano Lazzari; Cristiano Santos; Adriel Ziesemer; Lorena Anghel; Ricardo Reis (IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, 2007)

A New Transistor-Level Layout Generation Strategy for Static CMOS Circuits - Cristiano Lazzari; Cristiano Santos; Ricardo Reis (13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006, 2006)

Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study - Cristiano Lazzari; Ricardo A. L. Reis; Lorena Anghel (12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy, 2006)

Multiple Defect Tolerant Devices for Unreliable Future Nanotechnologies - Lorena Anghel; Cristiano Lazzari; Michael Nicolaidis (7th Latin American Test Workshop, LATW 2006, Buenos Aires, Argentina, March 26-29, 2006, 2006)

On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study - Cristiano Lazzari; Lorena Anghel; Ricardo A. L. Reis (11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, 2005)

A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming - Cristiano Lazzari; Lorena Anghel; Ricardo Reis (VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia, 2005)

Automatic Full-Custom Layout Generation of Static CMOS Circuits Targeting Delay and Power Reduction - Cristiano Lazzari (Student Forum, IFIP 18th World Computer Congress - Student Forum, 22-27 August 2004, Toulouse, France, 2004)

A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool - Fabricio B. Bastian; Cristiano Lazzari; José Luís Almada Güntzel; Ricardo Reis (Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, 2004)

A Transistor Sizing Method Applied to an Automatic Layout Generation Tool - Cristiano Santos; Gustavo Wilke; Cristiano Lazzari; Ricardo Reis; José Luís Almada Güntzel (Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003, 2003)

A New Macro-cell Generation Strategy for three metal layer CMOS Technologies - Cristiano Lazzari; Cristiano Viana Domingues; José Luís Almada Güntzel; Ricardo Augusto da Luz Reis (IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003, 2003)

A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits - Cristiano Lazzari; Cristiano Viana Domingues; José Luís Güntzel; Ricardo Reis (VLSI-SOC: From Systems to Chips - IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany, 2003)