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2020 – today
- 2022
[j9]Chi-Hsiang Huang
, Yidong Chen, Xun Sun, Arindam Mandal, Venkata Rajesh Pamula, Nasser A. Kurd, Visvesh S. Sathe:
Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control. IEEE J. Solid State Circuits 57(1): 90-102 (2022)- [j8]Hao Luo, Somnath Kundu, Timo Huusari, Sarah Shahraini, Eduardo Alban, Jason Mix, Nasser A. Kurd, Mohamed Abdel-Moneum, Brent R. Carlton:
A Fast Startup Crystal Oscillator Using Impedance Guided Chirp Injection in 22 nm FinFET CMOS. IEEE J. Solid State Circuits 57(3): 688-697 (2022) - [c14]Somnath Kundu, Timo Huusari, Hao Luo, Abhishek Agrawal, Eduardo Alban, Sarah Shahraini, Thao Xiong, Dan Lake, Stefano Pellerano, Jason Mix, Nasser A. Kurd, Mohamed Abdel-moneum, Brent R. Carlton:
A 2-to-2.48GHz Voltage-Interpolator-Based Fractional-N Type-I Sampling PLL in 22nm FinFET Assisting Fast Crystal Startup. ISSCC 2022: 144-146 - 2021
- [c13]Hao Luo, Somnath Kundu, Chun C. Lee, Rinkle Jain, Sarah Shahraini, Eduardo Alban, Timo Huusari, Jason Mix, Nasser A. Kurd, Mohamed Abdel-moneum, Brent R. Carlton:
A 12MHz/38.4MHz Fast Start-Up Crystal Oscillator using Impedance Guided Chirp Injection in 22nm FinFET CMOS. CICC 2021: 1-2 - [c12]Praveen Mosalikanti, Qi Wang, Kuan-Yueh James Shen, Mark Neidengard, Syed Feruz Syed Farooq, Vaughn Grossnickle, Nasser A. Kurd:
29.3 80ns Fast-Lock 0.4-to-6.5GHz Clock Generator with Self- Referenced Asynchronous Adaptive Droop Mitigation. ISSCC 2021: 408-410
2010 – 2019
- 2018
- [j7]Kuan-Yueh James Shen, Syed Feruz Syed Farooq, Yongping Fan, Khoa Minh Nguyen, Qi Wang, Mark Neidengard, Nasser A. Kurd, Amr Elshazly:
A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(7): 2109-2117 (2018) - 2016
- [j6]Takao Oshita, Joseph Shor, David E. Duarte, Avner Kornfeld, George L. Geannopoulos, Jonathan Douglas, Nasser A. Kurd:
A Compact First-Order ΣΔ Modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process. IEEE J. Solid State Circuits 51(2): 378-390 (2016) - [c11]Kuan-Yueh James Shen, Syed Feruz Syed Farooq, Yongping Fan, Khoa Minh Nguyen, Qi Wang, Amr Elshazly, Nasser A. Kurd:
19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS. ISSCC 2016: 330-331 - 2015
- [j5]Nasser A. Kurd, Muntaquim Chowdhury, Edward Burton, Thomas P. Thomas, Christopher Mozak, Brent Boswell, Praveen Mosalikanti, Mark Neidengard, Anant Deval, Ashish Khanna, Nasirul Chowdhury, Ravi Rajwar, Timothy M. Wilson, Rajesh Kumar:
Haswell: A Family of IA 22 nm Processors. IEEE J. Solid State Circuits 50(1): 49-58 (2015) - [c10]Amr Lotfy, Syed Feruz Syed Farooq, Qi S. Wang, Soner Yaldiz, Praveen Mosalikanti, Nasser A. Kurd:
A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology. CICC 2015: 1-4 - [c9]Praveen Mosalikanti, Nasser A. Kurd, Christopher Mozak, Takao Oshita:
Low power analog circuit techniques in the 5th generation intel coreTM microprocessor (broadwell). CICC 2015: 1-4 - [c8]Ankireddy Nalamalpu, Nasser A. Kurd, Anant Deval, Christopher Mozak, Jonathan Douglas, Ashish Khanna, Fabrice Paillet, Gerhard Schrom, Boyd Phelps:
Broadwell: A family of IA 14nm processors. VLSIC 2015: 314- - 2014
- [c7]Nasser A. Kurd, Muntaquim Chowdhury, Edward Burton, Thomas P. Thomas, Christopher Mozak, Brent Boswell, Manoj Lal, Anant Deval, Jonathan Douglas, Ali M. El-Husseini, Ankireddy Nalamalpu, Timothy M. Wilson, Matthew Merten, Srinivas Chennupaty, Wilfred Gomes, Rajesh Kumar:
5.9 Haswell: A family of IA 22nm processors. ISSCC 2014: 112-113 - 2012
- [c6]Moataz Abdelfattah, Maged Ghoneima, Yehea I. Ismail, Amr Lotfy, Mohamed Abdel-moneum, Nasser A. Kurd, Greg Taylor:
Modeling the response of Bang-Bang digital PLLs to phase error perturbations. CICC 2012: 1-4 - [c5]Moataz Abdelfattah, Maged Ghoneima, Yehea I. Ismail, Amr Lotfy, Mohamed Abdelsalam, Mohamed Abdel-moneum, Nasser A. Kurd, Greg Taylor:
A novel digital loop filter architecture for bang-bang ADPLL. SoCC 2012: 45-50 - [c4]Nasirul Chowdhury, Jeff Wight, Christopher Mozak, Nasser A. Kurd:
Intel® Core™ i5/i7 QuickPath Interconnect receiver clocking circuits and training algorithm. VLSI-DAT 2012: 1-4 - 2011
- [j4]Nasser A. Kurd, Subramani Bhamidipati, Christopher Mozak, Jeffrey L. Miller, Praveen Mosalikanti, Timothy M. Wilson, Ali M. El-Husseini, Mark Neidengard, Ramy E. Aly, Mahadev Nemani, Muntaquim Chowdhury, Rajesh Kumar:
A Family of 32 nm IA Processors. IEEE J. Solid State Circuits 46(1): 119-130 (2011) - 2010
- [c3]Nasser A. Kurd, Subramani Bhamidipati, Christopher Mozak, Jeffrey L. Miller, Timothy M. Wilson, Mahadev Nemani, Muntaquim Chowdhury:
Westmere: A family of 32nm IA processors. ISSCC 2010: 96-97
2000 – 2009
- 2009
- [j3]Nasser A. Kurd, Praveen Mosalikanti, Mark Neidengard, Jonathan Douglas, Rajesh Kumar:
Next Generation Intel¯ Core™ Micro-Architecture (Nehalem) Clocking. IEEE J. Solid State Circuits 44(4): 1121-1129 (2009) - 2008
- [j2]Maged Ghoneima, Muhammad M. Khellah, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail, Vivek K. De:
Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(7): 1904-1910 (2008) - 2007
- [c2]James W. Tschanz, Nam-Sung Kim, Saurabh Dighe, Jason Howard, Gregory Ruhl, Sriram R. Vangal, Siva G. Narendra, Yatin Hoskote, Howard Wilson, Carol Lam, Matthew Shuman, Carlos Tokunaga, Dinesh Somasekhar, Stephen Tang, David Finan, Tanay Karnik, Nitin Borkar, Nasser A. Kurd, Vivek De:
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. ISSCC 2007: 292-604 - 2005
- [c1]Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail:
A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. ICCD 2005: 253-257 - 2001
- [j1]Nasser A. Kurd, Javed S. Barkatullah, Rommel O. Dizon, Thomas D. Fletcher, Paul D. Madland:
A multigigahertz clocking scheme for the Pentium(R) 4 microprocessor. IEEE J. Solid State Circuits 36(11): 1647-1653 (2001)
Coauthor Index
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