Practical Approaches to Industrializing Near-THz Communication Systems. - Shahramian, Shahriar; Sayginer, Mustafa; Holyoak, Michael J.; Elkhouly, Mohamed; Zierdt, Mike; Ha, Jaegeun; Weiner, Joe; Baeyens, Yves (2023)

Fully Integrated 2D Scalable TX/RX Chipset for D-Band Phased-Array-on-Glass Modules. - Elkhouly, Mohamed; Ha, Jaegeun; Holyoak, Michael J.; Hendry, David; Sayginer, Mustafa; Enright, Ryan; Kimionis, Ioannis; Baeyens, Yves; Shahramian, Shahriar (2022)

Guest Editorial Introduction to the Special Section on the 2020 IEEE BCICTS Conference. - Shahramian, Shahriar (IEEE J. Solid State Circuits, 2021)

Introduction to the Special Section on the 2018 IEEE BCICTS Conference. - Shahramian, Shahriar (IEEE J. Solid State Circuits, 2019)

A Fully Integrated 384-Element, 16-Tile, $W$ -Band Phased Array With Self-Alignment and Self-Test. - Shahramian, Shahriar; Holyoak, Michael J.; Singh, Amit; Baeyens, Yves (IEEE J. Solid State Circuits, 2019)

Introduction to the Special Section on the 2017 IEEE BCTM and IEEE CSICS Conferences. - Wang, Hua; Shahramian, Shahriar (IEEE J. Solid State Circuits, 2018)

A fully integrated scalable W-band phased-array module with integrated antennas, self-alignment and self-test. - Shahramian, Shahriar; Holyoak, Mike; Singh, Amit; Farahani, Bahar Jalali; Baeyens, Yves (2018)

Introduction to the Special Section on the 2015 Compound Semiconductor Integrated Circuit Symposium. - Shahramian, Shahriar (IEEE J. Solid State Circuits, 2016)

Demonstration of 112-Gbit/s optical transmission using 56GBaud PAM-4 driver and clock-and-data recovery ICs. - Lee, Jeffrey; Shahramian, Shahriar; Kaneda, Noriaki; Baeyens, Yves; Sinsky, Jeffrey H.; Buhl, Lawrence L.; Weiner, Joe; Koc, Ut-Va; Konczykowska, Agnieszka; Dupuy, Jean-Yves; Jorge, Filipe; Aroca, Ricardo; et al. (2015)

A 70-100 GHz Direct-Conversion Transmitter and Receiver Phased Array Chipset Demonstrating 10 Gb/s Wireless Link. - Shahramian, Shahriar; Baeyens, Yves; Kaneda, Noriaki; Chen, Young-Kai (IEEE J. Solid State Circuits, 2013)

Design of a Dual W- and D-Band PLL. - Shahramian, Shahriar; Hart, Adam; Tomkins, Alexander; Carusone, Anthony Chan; Garcia, Patrice; Chevalier, Pascal; Voinigescu, Sorin P. (IEEE J. Solid State Circuits, 2011)

A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees. - Shahramian, Shahriar; Voinigescu, Sorin P.; Carusone, Anthony Chan (IEEE J. Solid State Circuits, 2009)

Design Methodology for a 40-GSamples/s Track and Hold Amplifier in 0.18-$muhbox m$SiGe BiCMOS Technology. - Shahramian, Shahriar; Carusone, Anthony Chan; Voinigescu, Sorin P. (IEEE J. Solid State Circuits, 2006)

A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology. - Shahramian, Shahriar; Voinigescu, Sorin P.; Carusone, Anthony Chan (2006)

Hardware reduction by combining pipelined A/D conversion and FIR filtering for channel equalization. - Shahramian, Shahriar; Carusone, Tony Chan (2004)