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ORCIDMasafumi Nogawa
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2010 – 2019
- 2017
[c7]Tomonori Tanaka, Kosuke Furuichi, Hiromu Uemura, Ryosuke Noguchi, Natsuyuki Koda, Koki Arauchi, Daichi Omoto, Hiromi Inaba, Keiji Kishine, Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka
:
25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS. ISCAS 2017: 1-4- 2015
- [c6]Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka, Akira Tsuchiya, Hidetoshi Onodera, Shunji Kimura:
A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking. A-SSCC 2015: 1-4 - 2014
- [c5]Shinsuke Nakano, Hiroaki Katsurai, Minoru Togashi, Hiroshi Koizumi, Masafumi Nogawa:
20.1-mW 8-Gbps UWB-IR millimeter-wave transmitter using an OOK pulse modulator based on CMOS inverters. ISCAS 2014: 2696-2699 - 2013
- [j6]Atsushi Kanda, Akira Ohki, Takeshi Kurosaki, Hiroaki Sanjoh, Kota Asaka, Ryoko Yoshimura, Toshio Ito, Makoto Nakamura, Masafumi Nogawa, Yusuke Ohtomo, Mikio Yoneyama:
Small and Low-Cost Dual-Rate Optical Triplexer for OLT Transceivers in 10G/1G Co-existing 10G-EPON Systems. IEICE Trans. Electron. 96-C(7): 996-1002 (2013) - [c4]Ichiro Fujimori, Masafumi Nogawa:
Session 7 overview: Optical transceivers and silicon photonics. ISSCC 2013: 114-115 - [c3]Elad Alon, Azita Emami, Gerrit den Besten, Ichiro Fujimori, Tadahiro Kuroda, Masafumi Nogawa, Hisakatsu Yamaguchi:
F3: Emerging technologies for wireline communication. ISSCC 2013: 504-505 - 2012
- [c2]Hiroshi Koizumi, Minoru Togashi, Masafumi Nogawa, Yusuke Ohtomo:
A 10Gb/s burst-mode laser diode driver for burst-by-burst power saving. ISSCC 2012: 414-416
2000 – 2009
- 2008
- [j5]Yusuke Ohtomo, Hiroshi Koizumi, Kazuyoshi Nishimura, Masafumi Nogawa:
A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI. IEICE Trans. Electron. 91-C(4): 655-661 (2008) - [j4]Yusuke Ohtomo, Masafumi Nogawa, Kazuyoshi Nishimura, Shunji Kimura, Tomoaki Yoshida, Tomoaki Kawamura, Minoru Togashi, Kiyomi Kumozaki:
A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs. IEICE Trans. Electron. 91-C(6): 903-910 (2008) - 2006
- [j3]Yusuke Ohtomo, Kazuyoshi Nishimura, Masafumi Nogawa:
A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS. IEEE J. Solid State Circuits 41(9): 2052-2057 (2006) - [c1]Masafumi Nogawa, Yusuke Ohtomo, Shunji Kimura, Kazuyoshi Nishimura, Tomoaki Kawamura, Minoru Togashi:
A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13µm CMOS. ISSCC 2006: 940-949
1990 – 1999
- 1998
- [j2]Masafumi Nogawa, Yusuke Ohtomo:
A data-transition look-ahead DFF circuit for statistical reduction in power consumption. IEEE J. Solid State Circuits 33(5): 702-706 (1998) - 1994
- [j1]Yusuke Ohtomo, Sadayuki Yasuda, Minoru Togashi, Massyuki Ino, Yasuyuki Tanabe, Jun-ichi Inoue, Masafumi Nogawa, Sshigeki Hino:
BiCMOS circuit technology for a 704 MHz ATM switch LSI. IEEE J. Solid State Circuits 29(5): 557-563 (1994)
Coauthor Index
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